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71V2556S150PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
6.4214
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
zHM661zHM051zHM331zHM001
lobmySretemaraP.niM.xaM.niM.xaM.niM.xaM.niM.xaMtinU
t
CYC
emiTelcyCkcolC6
____
7.6
____
5.7
____
01
____
sn
t
F
)1(
ecneuqerFkcolC
____
661
____
051
____
331
____
001zHM
t
HC
)2(
htdiWesluPhgiHkcolC8.1
____
0.2
____
2.2
____
2.3
____
sn
t
LC
)2(
htdiWesluPwoLkcolC8.1
____
0.2
____
2.2
____
2.3
____
sn
sretemaraPtuptuO
t
DC
ataDdilaVothgiHkcolC
____
5.3
____
8.3
____
2.4
____
5sn
t
CDC
egnahCataDothgiHkcolC1
____
1
____
1
____
1
____
sn
t
ZLC
)5,4,3(
evitcAtuptuOothgiHkcolC1
____
1
____
1
____
1
____
sn
t
ZHC
)5,4,3(
Z-hgiHataDothgiHkcolC 13131313sn
t
EO
emiTsseccAelbanEtuptuO
____
5.3
____
8.3
____
2.4
____
5sn
t
ZLO
)4,3(
evitcAataDotwoLelbanEtuptuO0
____
0
____
0
____
0
____
sn
t
ZHO
)4,3(
Z-hgiHataDothgiHelbanEtuptuO
____
5.3
____
8.3
____
2.4
____
5sn
semiTpUteS
t
ES
emiTputeSelbanEkcolC5.1
____
5.1
____
7.1
____
0.2
____
sn
t
AS
emiTputeSsserddA5.1
____
5.1
____
7.1
____
0.2
____
sn
t
DS
emiTputeSnIataD5.1
____
5.1
____
7.1
____
0.2
____
sn
t
WS
/R(etirW/daeR W emiTputeS)5.1
____
5.1
____
7.1
____
0.2
____
sn
t
VDAS
/VDA(daoL/ecnavdA DL puteS)
emiT
5.1
____
5.1
____
7.1
____
0.2
____
sn
t
CS
emiTputeStceleS/elbanEpihC5.1
____
5.1
____
7.1
____
0.2
____
sn
t
BS
(elbanEetirWetyB WB puteS)x
emiT
5.1
____
5.1
____
7.1
____
0.2
____
sn
semiTdloH
t
EH
emiTdloHelbanEkcolC5.0
____
5.0
____
5.0
____
5.0
____
sn
t
AH
emiTdloHsserddA5.0
____
5.0
____
5.0
____
5.0
____
sn
t
DH
emiTdloHnIataD5.0
____
5.0
____
5.0
____
5.0
____
sn
t
WH
/R(etirW/daeR W emiTdloH)5.0
____
5.0
____
5.0
____
5.0
____
sn
t
VDAH
/VDA(daoL/ecnavdA DL emiTdloH)5.0
____
5.0
____
5.0
____
5.0
____
sn
t
CH
emiTdloHtceleS/elbanEpihC5.0
____
5.0
____
5.0
____
5.0
____
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t
BH
(elbanEetirWetyB WB emiTdloH)x5.0
____
5.0
____
5.0
____
5.0
____
sn
42lbt5784
6.42
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
15
Timing Waveform of Read Cycle
(1,2,3,4)
NOTES:
1. Q (A
1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A
2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
ADV/LD
(CEN high, eliminates
current L-H clock edge)
O2(A2)
t
CD
t
HADV
Pipeline
Read
(Burst Wraps around
to initial state)
t
CDC
t
CLZ
t
CHZ
t
CD
t
CDC
R/W
CLK
CEN
ADDRESS
OE
DATA
OUT
t
HE
t
SE
A1
A2
O1(A2)
t
CH
t
CL
t
CYC
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
Burst Pipeline Read
Pipeline
Read
BW
1
- BW
4
4875 drw 06
CE
1
,
CE
2
(2)
Q(A
2+3
)
Q(A
2
)
Q(A
2+2
)
Q(A
2+2
)Q(A
2+1
)
Q(A
2
)
Q(A
1
)
6.4216
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. D (A
1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A
2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
Timing Waveform of Write Cycles
(1,2,3,4,5)
t
HE
t
SE
R/W
A
1
A
2
CLK
C EN
ADV/LD
ADDRESS
O E
DATA
IN
t
HD
t
SD
t
CH
t
CL
t
CYC
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
Burst Pipeline Write
Pipeline
Write
Pipeline
Write
t
HB
t
SB
(Burst Wraps around
to initial state)
t
HD
t
SD
(CEN high, eliminates
current L-H clock edge)
(2)
D(
A2+2
)
D(
A2+3
)
D(A
1
)
D(A
2
)
D(A
2
)
4875 drw 07
BW 1 - BW 4
C E1, C E2
D(A
2+1
)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

71V2556S150PFG

Mfr. #:
Buy 71V2556S150PFG
Manufacturer:
IDT
Description:
SRAM 4M X36 2.5V I/O SLOW ZBT
Lifecycle:
New from this manufacturer.
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