OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

71V2556S150PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
6.428
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
Functional Timing Diagram
(1)
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
n+29
A29
C29
D/Q27
ADDRESS
(2)
(A0 - A16)
CONTROL
(2)
(R/W , ADV/LD , BW x)
DATA
(2)
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q28
n+31
A31
C31
D/Q29
n+32
A32
C32
D/Q30
n+33
A33
C33
D/Q31
n+34
A34
C34
D/Q32
n+35
A35
C35
D/Q33
n+36
A36
C36
D/Q34
n+37
A37
C37
D/Q35
4875 drw 03
,
1ecneuqeS2ecneuqeS3ecneuqeS4ecneuqeS
1A0A1A0A1A0A1A0A
sserddAtsriF 00011011
sserddAdnoceS01101100
sserddAdrihT 10110001
sserddAhtruoF
)1(
11000110
11lbt5784
1ecneuqeS2ecneuqeS3ecneuqeS4ecneuqeS
1A0A1A0A1A0A1A0A
sserddAtsriF 00011011
sserddAdnoceS 01001110
sserddAdrihT 10110001
sserddAhtruoF
)1(
11100100
01lbt5784
6.42
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
9
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Read Operation
(1)
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles
(2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
elcyCsserddA/R W /VDA DL
EC
)1(
NECWB x EO
O/IstnemmoC
nA
0
H L LLXXX daerdaoL
1+n X X H XLXXX daertsruB
2+nA
1
HL LLXLQ
0
daerdaoL
3+nXXLHLXLQ
1+0
POTSrotceleseD
4+n X X H XLXLQ
1
POON
5+nA
2
HL LLXXZ daerdaoL
6+nXXHXLXXZ daertsruB
7+nXXLHLXLQ
2
POTSrotceleseD
8+nA
3
L L LLLLQ
1+2
etirwdaoL
9+nXXHXLLXZ etirwtsruB
01+nA
4
L L LLLXD
3
etirwdaoL
11+nXXLHLXXD
1+3
POTSrotceleseD
21+nXXHXLXXD
4
POON
31+nA
5
L L LLLXZ etirwdaoL
41+nA
6
HL LLXXZ daerdaoL
51+nA
7
L L LLLXD
5
etirwdaoL
61+n X X H XLLLQ
6
etirwtsruB
71+nA
8
HL LLXXD
7
daerdaoL
81+nXXHXLXXD
1+7
daertsruB
91+nA
9
L L LLLLQ
8
etirwdaoL
21lbt5784
elcyCsserddA/R W /VDA DL
EC
)2(
NECWB x EO
O/IstnemmoC
nA
0
H L LLXXX putesteemlortnoCdnasserddA
1+n X X X XLXXX dilaVputeSkcolC
2+n X X X XXXLQ
0
AsserddAfostnetnoC
0
tuOdaeR
31lbt5784
6.4210
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Burst Write Operation
(1)
Burst Read Operation
(1)
Write Operation
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
elcyCsserddA/R W /VDA DL
EC
)2(
NECWB x EO
O/IstnemmoC
nA
0
H L LLXXX putesteemlortnoCdnasserddA
1+n X X H XLXXX retnuoCecnavdA,dilaVputeSkcolC
2+n X X H XLXLQ
0
AsserddA
0
tnuoC.cnI,tuOdaeR
3+n X X H XLXLQ
1+0
AsserddA
1+0
tnuoC.cnI,tuOdaeR
4+n X X H XLXLQ
2+0
AsserddA
2+0
tnuoC.cnI,tuOdaeR
5+nA
1
HL LLXLQ
3+0
AsserddA
3+0
AdaoL,tuOdaeR
1
6+n X X H XLXLQ
0
AsserddA
0
tnuoC.cnI,tuOdaeR
7+n X X H XLXLQ
1
AsserddA
1
tnuoC.cnI,tuOdaeR
8+nA
2
HL LLXLQ
1+1
AsserddA
1+1
AdaoL,tuOdaeR
2
41lbt5784
elcyCsserddA/R W /VDA DL
EC
)2(
NECWB x EO
O/IstnemmoC
nA
0
L L LLLXX putesteemlortnoCdnasserddA
1+n X X X XLXXX dilaVputeSkcolC
2+nXXXXLXXD
0
AsserddAotetirW
0
51lbt5784
elcyCsserddA/R W /VDA DL
EC
)2(
NECWB x EO
O/IstnemmoC
nA
0
L L LLLXX putesteemlortnoCdnasserddA
1+nXXHXLLXX tnuoC.cnI,dilaVputeSkcolC
2+nXXHXLLXD
0
sserddAA
0
tnuoC.cnI,etirW
3+nXXHXLLXD
1+0
AsserddA
1+0
tnuoC.cnI,etirW
4+nXXHXLLXD
2+0
AsserddA
2+0
tnuoC.cnI,etirW
5+n1A L L LLLXD
3+0
AsserddA
3+0
daoL,etirWA
1
6+nXXHXLLXD
0
AsserddA
0
tnuoC.cnI,etirW
7+nXXHXLLXD
1
AsserddA
1
tnuoC.cnI,etirW
8+nA
2
L L LLLXD
1+1
AsserddA
1+1
AdaoL,etirW
2
61lbt5784
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

71V2556S150PFG

Mfr. #:
Buy 71V2556S150PFG
Manufacturer:
IDT
Description:
SRAM 4M X36 2.5V I/O SLOW ZBT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet