LPC2468 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 11 January 2013 7 of 85
NXP Semiconductors
LPC2468
Single-chip 16-bit/32-bit micro
Row H
1 P0[23]/AD0[0]/
I2SRX_CLK/CAP3[0]
2 P3[14]/D14 3 P3[30]/D30/
MAT1[1]/RTS1
4V
DD(DCDC)(3V3)
14 V
SSIO
15 P2[8]/TD2/
TXD2/TRACEPKT3
16 P2[9]/
USB_CONNECT1/
RXD2/EXTIN0
17 P4[9]/A9
Row J
1 P3[6]/D6 2 V
SSA
3 P3[31]/D31/MAT1[2] 4 n.c.
14 P0[16]/RXD1/
SSEL0/SSEL
15 P4[23]/A23/
RXD2/MOSI1
16 P0[15]/TXD1/
SCK0/SCK
17 P4[8]/A8
Row K
1 VREF 2 RTCX1 3 RSTOUT
4V
SSCORE
14 P4[22]/A22/
TXD2/MISO1
15 P0[18]/DCD1/
MOSI0/MOSI
16 V
DD(3V3)
17 P0[17]/CTS1/
MISO0/MISO
Row L
1 P3[7]/D7 2 RTCX2 3 V
SSIO
4 P2[30]/DQMOUT2/
MAT3[2]/SDA2
14 n.c. 15 P4[26]/BLS0
16 P4[7]/A7 17 P0[19]/DSR1/
MCICLK/SDA1
Row M
1 P3[15]/D15 2 RESET
3 VBAT 4 XTAL1
14 P4[6]/A6 15 P4[21]/A21/
SCL2/SSEL1
16 P0[21]/RI1/
MCIPWR/RD1
17 P0[20]/DTR1/
MCICMD/SCL1
Row N
1 ALARM 2 P2[31]/DQMOUT3/
MAT3[3]/SCL2
3 P2[29]/DQMOUT1 4 XTAL2
14 P2[12]/EINT2
/
MCIDAT2/I2STX_WS
15 P2[10]/EINT0 16 V
SSIO
17 P0[22]/RTS1/
MCIDAT0/TD1
Row P
1 P1[31]/USB_OVRCR2
/
SCK1/AD0[5]
2 P1[30]/USB_PWRD2/
V
BUS
/AD0[4]
3 P2[27]/CKEOUT3/
MAT3[1]/MOSI0
4 P2[28]/DQMOUT0
5 P2[24]/CKEOUT0 6 V
DD(3V3)
7 P1[18]/USB_UP_LED1/
PWM1[1]/CAP1[0]
8V
DD(3V3)
9 P1[23]/USB_RX_DP1/
PWM1[4]/MISO0
10 V
SSCORE
11 V
DD(DCDC)(3V3)
12 V
SSIO
13 P2[15]/CS3/
CAP2[1]/SCL1
14 P4[17]/A17 15 P4[18]/A18 16 P4[19]/A19
17 V
DD(3V3)
---
Row R
1 P0[12]/USB_PPWR2
/
MISO1/AD0[6]
2 P0[13]/USB_UP_LED2/
MOSI1/AD0[7]
3 P0[28]/SCL0 4 P2[25]/CKEOUT1
5 P3[24]/D24/
CAP0[1]/PWM1[1]
6 P0[30]/USB_D1 7 P2[19]/CLKOUT1 8 P1[21]/USB_TX_DM1/
PWM1[3]/SSEL0
9V
SSIO
10 P1[26]/USB_SSPND1/
PWM1[6]/CAP0[0]
11 P2[16]/CAS 12 P2[14]/CS2/
CAP2[0]/SDA1
Table 3. Pin allocation table
…continued
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
LPC2468 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 11 January 2013 8 of 85
NXP Semiconductors
LPC2468
Single-chip 16-bit/32-bit micro
6.2 Pin description
13 P2[17]/RAS 14 P0[11]/RXD2/SCL2/
MAT3[1]
15 P4[4]/A4 16 P4[5]/A5
17 P4[20]/A20/
SDA2/SCK1
---
Row T
1 P0[27]/SDA0 2 P0[31]/USB_D+2 3 P3[26]/D26/
MAT0[1]/PWM1[3]
4 P2[26]/CKEOUT2/
MAT3[0]/MISO0
5V
SSIO
6 P3[23]/D23/
CAP0[0]/PCAP1[0]
7 P0[14]/USB_HSTEN2/
USB_CONNECT2/
SSEL1
8 P2[20]/DYCS0
9 P1[24]/USB_RX_DM1/
PWM1[5]/MOSI0
10 P1[25]/USB_LS1/
USB_HSTEN1/MAT1[1]
11 P4[2]/A2 12 P1[27]/USB_INT1/
USB_OVRCR1/CAP0[1]
13 P1[28]/USB_SCL1/
PCAP1[0]/MAT0[0]
14 P0[1]/TD1/RXD3/SCL1 15 P0[10]/TXD2/SDA2/
MAT3[0]
16 P2[13]/EINT3
/
MCIDAT3/I2STX_SDA
17 P2[11]/EINT1
/
MCIDAT1/I2STX_CLK
---
Row U
1 USB_D22P3[25]/D25/
MAT0[0]/PWM1[2]
3 P2[18]/CLKOUT0 4 P0[29]/USB_D+1
5 P2[23]/DYCS3
/
CAP3[1]/SSEL0
6 P1[19]/USB_TX_E1/
USB_PPWR1
/CAP1[1]
7 P1[20]/USB_TX_DP1/
PWM1[2]/SCK0
8 P1[22]/USB_RCV1/
USB_PWRD1/MAT1[0]
9 P4[0]/A0 10 P4[1]/A1 11 P2[21]/DYCS1
12 P2[22]/DYCS2/
CAP3[0]/SCK0
13 V
DD(3V3)
14 P1[29]/USB_SDA1/
PCAP1[1]/MAT0[1]
15 P0[0]/RD1/TXD3/SDA1 16 P4[3]/A3
17 P4[16]/A16 - - -
Table 3. Pin allocation table …continued
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Table 4. Pin description
Symbol Pin Ball Type Description
P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for
each bit. The operation of port 0 pins depends upon the pin function
selected via the Pin Connect block.
P0[0]/RD1/
TXD3/SDA1
94
[1]
U15
[1]
I/O P0[0] — General purpose digital input/output pin.
I RD1 — CAN1 receiver input.
O TXD3 — Transmitter output for UART3.
I/O SDA1 — I
2
C1 data input/output (this is not an open-drain pin).
P0[1]/TD1/RXD3/
SCL1
96
[1]
T14
[1]
I/O P0[1] — General purpose digital input/output pin.
O TD1 — CAN1 transmitter output.
I RXD3 — Receiver input for UART3.
I/O SCL1 — I
2
C1 clock input/output (this is not an open-drain pin).
P0[2]/TXD0 202
[1]
C4
[1]
I/O P0[2] — General purpose digital input/output pin.
O TXD0 — Transmitter output for UART0.
LPC2468 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 11 January 2013 9 of 85
NXP Semiconductors
LPC2468
Single-chip 16-bit/32-bit micro
P0[3]/RXD0 204
[1]
D6
[1]
I/O P0[3] — General purpose digital input/output pin.
I RXD0 — Receiver input for UART0.
P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
168
[1]
B12
[1]
I/O P0[4] — General purpose digital input/output pin.
I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I
2
S-bus specification.
I RD2 — CAN2 receiver input.
I CAP2[0] — Capture input for Timer 2, channel 0.
P0[5]/
I2SRX_WS/
TD2/CAP2[1]
166
[1]
C12
[1]
I/O P0[5] — General purpose digital input/output pin.
I/O I2SRX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I
2
S-bus
specification.
O TD2 — CAN2 transmitter output.
I CAP2[1] — Capture input for Timer 2, channel 1.
P0[6]/
I2SRX_SDA/
SSEL1/MAT2[0]
164
[1]
D13
[1]
I/O P0[6] — General purpose digital input/output pin.
I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I
2
S-bus specification.
I/O SSEL1 — Slave Select for SSP1.
O MAT2[0] — Match output for Timer 2, channel 0.
P0[7]/
I2STX_CLK/
SCK1/MAT2[1]
162
[1]
C13
[1]
I/O P0[7] — General purpose digital input/output pin.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I
2
S-bus specification.
I/O SCK1 — Serial Clock for SSP1.
O MAT2[1] — Match output for Timer 2, channel 1.
P0[8]/
I2STX_WS/
MISO1/MAT2[2]
160
[1]
A15
[1]
I/O P0[8] — General purpose digital input/output pin.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I
2
S-bus
specification.
I/O MISO1 — Master In Slave Out for SSP1.
O MAT2[2] — Match output for Timer 2, channel 2.
P0[9]/
I2STX_SDA/
MOSI1/MAT2[3]
158
[1]
C14
[1]
I/O P0[9] — General purpose digital input/output pin.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I
2
S-bus specification.
I/O MOSI1 — Master Out Slave In for SSP1.
O MAT2[3] — Match output for Timer 2, channel 3.
P0[10]/TXD2/
SDA2/MAT3[0]
98
[1]
T15
[1]
I/O P0[10] — General purpose digital input/output pin.
O TXD2 — Transmitter output for UART2.
I/O SDA2 — I
2
C2 data input/output (this is not an open-drain pin).
O MAT3[0] — Match output for Timer 3, channel 0.
P0[11]/RXD2/
SCL2/MAT3[1]
100
[1]
R14
[1]
I/O P0[11] — General purpose digital input/output pin.
I RXD2 — Receiver input for UART2.
I/O SCL2 — I
2
C2 clock input/output (this is not an open-drain pin).
O MAT3[1] — Match output for Timer 3, channel 1.
Table 4. Pin description
…continued
Symbol Pin Ball Type Description

LPC2468FBD208,551

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 512KF/USBH/ENET
Lifecycle:
New from this manufacturer.
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