21
COMMERCIAL TEMPERATURE RANGE
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Figure 9. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA, FFC/IRC is set HIGH.
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
Figure 8. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
4665 drw09
CLKA
MRS1,
MRS2
FFA/IRA
CLKC
FFC/IRC
A0-A35
FS1,FS0
ENA
tFSH
tWFF
tENHtENS2
tSKEW1
tDS
tDH
tWFF
4
0,0
AFA Offset
(Y1)
AEB Offset
(X1)
AFC Offset
(Y2)
AEA Offset
(X2)
First Word to FIFO1
1
2
(1)
tFSH
tFSS
tFSS
FS2
CLKA
FFA/IRA
t
SENS
t
SENH
FS0/SD
(3)
t
SPH
t
SENS
t
SENH
t
FSS
t
WFF
FS1/SEN
AEA Offset
(X2) LSB
t
SDS
t
SDH
t
SDS
t
SDH
AFA Offset
(Y1) MSB
MRS1,
MRS2
4
4665 drw 10
t
FSS
t
FSH
CLKC
4
FS2
FFC/IRC
t
WFF
t
SKEW
(1)
