29
COMMERCIAL TEMPERATURE RANGE
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 20. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
CSB
MBB
RENB
B0-B17
CLKB
CLKA
CSA
4665 drw21
W/RA
12
A0-A35
MBA
ENA
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO1
Read 2
LOW
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
t
WFF
t
WFF
Read 1
t
A
Previous Word in
FIFO1 Output Register
ORB
IRA
Write
