31
COMMERCIAL TEMPERATURE RANGE
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKC edge for IRC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge and rising
CLKC edge is less than tSKEW1, then IRC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 22. IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
CSA
ORA
MBA
ENA
A0-A35
CLKA
IRC
CLKC
4665 drw23
12
C0-C17
MBC
WENC
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/RA
LOW
LOW
HIGH
(1)
FIFO2 Full
t
WFF
t
DH
t
DS
t
WFF
Write
32
COMMERCIAL TEMPERATURE RANGE
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 24. Timing for
AEBAEB
AEBAEB
AEB
when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
Figure 23.
FFCFFC
FFCFFC
FFC
Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKC edge for FFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge and rising
CLKC edge is less than tSKEW1, then FFC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
CSA
EFA
MBA
ENA
A0-A35
CLKA
FFC
CLKC
4665 drw24
12
C0-C17
MBC
ENC
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/RA
LOW
LOW
HIGH
(1)
FIFO2 Full
t
WFF
t
WFF
t
DH
t
DS
Write
AEB
CLKA
RENB
4665 drw 25
ENA
CLKB
2
1
tENS2
tENH
tSKEW2
tPAE
tPAE
tENS2
tENH
X1 Word in FIFO1
(X1+1) Words in FIFO1
(1)
33
COMMERCIAL TEMPERATURE RANGE
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKC cycle later than shown.
2. FIFO2 write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3656, 4,096 for the IDT72V3666, 8,192 for the IDT72V3676.
4. Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.
Figure 27. Timing for
AFCAFC
AFCAFC
AFC
when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
Figure 25. Timing for
AEAAEA
AEAAEA
AEA
when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
Figure 26. Timing for
AFAAFA
AFAAFA
AFA
when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3656, 4,096 for the IDT72V3666, 8,192 for the IDT72V3676.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
AEA
CLKC
ENA
4665 drw 26
WENC
CLKA
2
1
t
ENS2
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS2
t
ENH
(X2+1) Words in FIFO2
X2 Words in FIFO2
(1)
AFA
CLKA
RENB
4665 drw 27
ENA
CLKB
12
t
SKEW2
t
ENS2
t
ENH
t
PAF
t
ENS2
t
ENH
t
PAF
[D-(Y1+1)] Words in FIFO1
(D-Y1) Words in FIFO1
(1)
AFC
CLKC
ENA
4665 drw 28
WENC
CLKA
12
t
SKEW2
t
ENS2
t
ENH
t
PAF
t
ENS2
t
ENH
t
PAF
[D-(Y2+1)] Words in FIFO2
(D-Y2) Words in FIFO2
(1)

72V3656L15PF8

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 2KX36X2 TRIPLE BUS SYNC FIFO
Lifecycle:
New from this manufacturer.
Delivery:
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