LTC4213
11
4213f
supply transient dips below 1.97V of less than 80µs are
ignored.
ON Function
When V
ON
is below comparator COMP1’s threshold of
0.4V for 80µs, the device resets. The system leaves reset
mode if the ON pin rises above comparator COMP2’s
threshold of 0.8V and the UVLO condition is met. Leaving
reset mode, the GATE pin starts up after a t
DEBOUNCE
delay
of 60µs. When ON goes below 0.76V, the GATE shuts off
after a 5µs glitch filter delay. The output is discharged by
the external load when V
ON
is in between 0.4V to 0.8V. At
this state, the ON pin can re-enable the GATE if V
ON
exceeds 0.8V for more than 8µs. Alternatively, the device
resets if the ON pin is brought below 0.4V for 80µs. Once
reset, the GATE pin restarts only after the t
DEBOUNCE
60µs
delay at V
ON
rising above 0.8V. To protect the ON pin from
overvoltage stress due to supply transients, a series
resistor of greater than 10k is recommended when the ON
pin is connected directly to the supply. An external resis-
tive divider at the ON pin can be used with COMP2 to set
a supply undervoltage lockout value higher than the inter-
nal UVLO circuit. An RC filter can be implemented at the
ON pin to increase the powerup delay time beyond the
internal 60µs delay.
Gate Function
The GATE pin is held low in reset mode. 60µs after leaving
reset mode, the GATE pin is charged up by an internal
100µA current source. The circuit breaker arms when
V
GATE
> V
SENSEN
+ ∆V
GSARM
. In normal mode operation,
the GATE peak voltage is internally clamped to ∆V
GSMAX
above the SENSEN pin. When the circuit breaker trips, an
internal MOSFET shorts the GATE pin to GND, turning off
the external MOSFET.
READY Status
The READY pin is held low during reset and at startup. It
is pulled high by an external pullup resistor 50µs after the
circuit breaker arms. The READY pin pulls low if the circuit
breaker trips or the ON pin is pulled below 0.76V, or V
CC
drops below undervoltage lockout.
∆V
GSARM
and V
GSMAX
Each MOSFET has a recommended V
GS
drive voltage
where the channel is deemed fully enhanced and R
DSON
is
minimized. Driving beyond this recommended V
GS
volt-
age yields a marginal decrease in R
DSON
. At startup, the
gate voltage starts at ground potential. The GATE ramps
past the MOSFET threshold and the load current begins to
flow. When V
GS
exceeds ∆V
GSARM
, the circuit breaker is
armed and enabled. The chosen MOSFET should have a
recommended minimum V
GS
drive level that is lower than
∆V
GSARM
. Finally, V
GS
reaches a maximum at ∆V
GSMAX.
Trip and Reset Circuit Breaker
Figure 2 shows the timing diagram of V
GATE
and V
READY
after a fault condition. A tripped circuit breaker can be reset
either by cycling the V
CC
bias supply below UVLO thresh-
old or pulling ON below 0.4V for >t
RESET
. Figure 3 shows
the timing diagram for a tripped circuit breaker being reset
by the ON pin.
Calculating Current Limit
The fault current limit is determined by the R
DSON
of the
MOSFET and the circuit breaker voltage V
CB
.
I
V
R
LIMIT
CB
DSON
= ()2
The R
DSON
value depends on the manufacturer’s distribu-
tion, V
GS
and junction temperature. Short Kelvin-sense
connections between the MOSFET drain and source to
the LTC4213 SENSEP and SENSEN pins are strongly
recommended.
For a selected MOSFET, the nominal load limit current is
given by:
I
V
R
LIMIT NOM
CB NOM
DSON NOM
()
()
()
()= 3
The minimum load limit current is given by:
I
V
R
LIMIT MIN
CB MIN
DSON MAX
()
()
()
()= 4
APPLICATIO S I FOR ATIO
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