Data Sheet ADV7181D
Rev. A | Page 9 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD to GND 4 V
DVDD to GND
2.2 V
PVDD to GND 2.2 V
DVDDIO to GND 4 V
DVDDIO to AVDD −0.3 V to +0.3 V
PVDD to DVDD −0.3 V to +0.3 V
DVDDIO to PVDD −0.3 V to +2 V
DVDDIO to DVDD −0.3 V to +2 V
AVDD to PVDD −0.3 V to +2 V
AVDD to DVDD −0.3 V to +2 V
Digital Inputs to GND GND − 0.3 V to
DVDDIO + 0.3 V
Digital Outputs to GND GND − 0.3 V to
DVDDIO + 0.3 V
Analog Inputs to GND GND − 0.3 V to
AVDD + 0.3 V
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature (T
J MAX
)
125°C
Storage Temperature Range
−65°C to +150°C
Infrared Reflow, Soldering (20 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
REFLOW SOLDER
The ADV7181D is a Pb-free, environmentally friendly product.
It is manufactured using the most up-to-date materials and pro-
cesses. The coating on the leads of each device is 100% pure Sn
electroplate. The device is suitable for Pb-free applications and
can withstand surface-mount soldering at up to 255°C ± 5°C.
In addition, the ADV7181D is backward-compatible with
conventional SnPb soldering processes. This means that the
electroplated Sn coating can be soldered with Sn/Pb solder
pastes at conventional reflow temperatures of 220°C to 235°C.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part, turn off any
unused ADCs.
It is imperative that the recommended scripts be used for the
following high current modes: SCART, 720p, 1080i, and all
RGB graphic standards. Using the recommended scripts ensures
correct thermal performance. These scripts are available from
a local field applications engineer (FAE).
The junction temperature must always stay below the maximum
junction temperature (T
J
MAX
) of 125°C. The junction temperature
can be calculated by
T
J
= T
A MAX
+ (θ
JA
× W
MAX
)
where:
T
A MAX
= 85°C.
θ
JA
= 20.3°C / W.
W
MAX
= ((AV D D × I
AV DD
) + (DVDD × I
DVDD
) +
(DVDDIO × I
DVDDIO
) + (PVDD × I
PVDD
))
THERMAL RESISTANCE
Table 6 specifies the typical values for the junction-to-ambient
thermal resistance (θ
JA
) and the junction-to-case thermal resis-
tance
JC
) for an ADV7181D soldered on a 4-layer PCB with
solid ground plane.
Table 6. Thermal Resistance
Package Type θ
JA
1
θ
JC
Unit
64-Lead LFCSP (CP-64-3) 20.3 1.2 °C/W
1
In still air.
ESD CAUTION
ADV7181D Data Sheet
Rev. A | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
VS
63
FIELD/DE
62
P16
61
P17
60
P18
59
P19
58
DVDD
57
GND
56
HS_IN/CS_IN
55
VS_IN
54
SCLK
53
SDATA
52
ALSB
51
RESET
50
SOY
49
A
IN
10
47
A
IN
8
46
A
IN
7
45
A
IN
6
42
REFOUT
43
CML
44
CAPC2
48
A
IN
9
41
AVDD
40
CAPY2
39
CAPY1
37
A
IN
4
36
A
IN
3
35
A
IN
2
34
A
IN
1
33
SOG
38
A
IN
5
2
HS/CS
3
GND
4
DVDDIO
7
P13
6
P14
5
P15
1
INT
8
P12
9
SFL/SYNC_OUT
10
GND
12
P11
13
P10
14
P9
15
P8
16
P7
11
DVDDIO
17
P6
18
P5
19
P4
20
LLC
21
XTAL1
22
XTAL
23
DVDD
24
GND
25
P3
26
P2
27
P1
28
P0
29
PWRDWN
30
ELPF
31
PVDD
32
FB
PIN 1
ADV7181D
TOP VIEW
(Not to Scale)
09994-006
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type Description
1
INT
Output
Interrupt. This pin can be active low or active high. When SDP/CP status bits change,
this pin is triggered. The set of events that triggers an interrupt is under user control.
2 HS/CS Output Horizontal Synchronization Output Signal (HS). Available in SDP and CP modes.
Digital Composite Synchronization Signal (CS). Available in CP mode only.
3, 10, 24, 57 GND Ground Ground.
4, 11 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
28 to 25, 19 to 12,
8 to 5, 62 to 59
P0 to P19
Output
Video Pixel Output Port. See Table 10 and Table 11 for output configuration modes.
9 SFL/SYNC_OUT Output Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be
used to lock the subcarrier frequency when this decoder is connected to any Analog
Devices digital video encoder.
Sliced Synchronization Output Signal (SYNC_OUT). Available in CP mode only.
20 LLC Output Line-Locked Clock Output for Pixel Data. The range is 12.825 MHz to 75 MHz.
21 XTAL1 Output This pin should be connected to the 28.63636 MHz crystal or left unconnected if an
external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7181D.
In crystal mode, the crystal must be a fundamental crystal.
22 XTAL Input Input Pin for the 28.63636 MHz Crystal. This input can be overdriven by an external
3.3 V, 28.63636 MHz clock oscillator source to clock the ADV7181D.
23, 58 DVDD Power Digital Core Supply Voltage (1.8 V).
29
PWRDWN
Input Power-Down Input. A Logic 0 on this pin places the ADV7181D in power-down mode.
30 ELPF Output External Loop Filter Output. The recommended external loop filter must be connected
to this pin (see the Recommended External Loop Filter Components section).
31 PVDD Power PLL Supply Voltage (1.8 V).
32 FB Input Fast Blank Input. Fast switch between CVBS and RGB analog signals.
33 SOG Input Sync on Green Input. Used in embedded synchronization mode.
Data Sheet ADV7181D
Rev. A | Page 11 of 24
Pin No. Mnemonic Type Description
34 to 38, 45 to 49 A
IN
1 to A
IN
10 Input Analog Video Input Channels.
39, 40 CAPY1, CAPY2 Input ADC Capacitor Network. See Figure 9 for a recommended capacitor network for
these pins.
41 AVDD Power Analog Supply Voltage (3.3 V).
42 REFOUT Output Internal Voltage Reference Output. See Figure 9 for a recommended capacitor network
for this pin.
43 CML Output Common-Mode Level Pin for the Internal ADCs. See Figure 9 for a recommended
capacitor network for this pin.
44 CAPC2 Input ADC Capacitor Network. See Figure 9 for a recommended capacitor network for this pin.
50 SOY Input Sync on Luma Input. Used in embedded synchronization mode.
51
RESET
Input System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7181D circuitry.
52 ALSB Input This pin selects the I
2
C address for the ADV7181D control and VBI readback ports. When
set to Logic 0, this pin sets the address for a write to Control Port 0x40 and the readback
address for VBI Port 0x21. When set to Logic 1, this pin sets the address for a write to
Control Port 0x42 and the readback address for VBI Port 0x23.
53 SDATA Input/
Output
I
2
C Port Serial Data Input/Output Pin.
54 SCLK Input I
2
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
55 VS_IN Input Vertical Synchronization Input Signal. This pin can be configured in CP mode to extract
timing in a 5-wire mode.
56
HS_IN/CS_IN
Input
Horizontal Synchronization Input Signal (HS_IN). This pin can be configured in CP mode
to extract timing in a 5-wire mode.
Composite Synchronization Input Signal (CS_IN). This pin can be configured in CP mode
to extract timing in a 4-wire mode.
63 FIELD/DE Output Field Synchronization Output Signal (FIELD). Used in all interlaced video modes.
Data Enable Signal (DE). This pin can also be used as a data enable (DE) signal in CP mode
to allow direct connection to an HDMI/DVI transmitter IC.
64 VS Output Vertical Synchronization Output Signal (SDP and CP Modes).
EP Exposed Pad The exposed pad must be connected to GND.

ADV7181DWBCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD/HD Video Decoder
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union