Data Sheet ADV7181D
Rev. A | Page 7 of 24
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T
MIN
to T
MAX
= −40°C to +85°C,
unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.
Table 4.
Parameter
1
Symbol Description Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency 28.63636 MHz
Crystal Frequency Stability ±50 ppm
Horizontal Sync Input Frequency 14.8 110 kHz
LLC Frequency Range 12.825 75 MHz
I
2
C PORT
2
SCLK Frequency 400 kHz
SCLK Minimum Pulse Width High t
1
0.6 μs
SCLK Minimum Pulse Width Low t
2
1.3 μs
Hold Time (Start Condition) t
3
0.6 μs
Setup Time (Start Condition) t
4
0.6 μs
SDATA Setup Time t
5
100 ns
SCLK and SDATA Rise Time t
6
300 ns
SCLK and SDATA Fall Time t
7
300 ns
Setup Time (Stop Condition) t
8
0.6 μs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC Mark-Space Ratio t
9
:t
10
45:55 55:45
% duty
cycle
DATA AND CONTROL OUTPUTS
Data Output Transition Time
SDR (SDP)
3
t
11
Negative clock edge to start of valid data 3.6 ns
t
12
End of valid data to negative clock edge 2.4 ns
SDR (CP)
4
t
13
End of valid data to negative clock edge 2.8 ns
t
14
Negative clock edge to start of valid data 0.1 ns
DDR (CP)
4, 5
t
15
Positive clock edge to end of valid data −4 + T
LLC
/4 ns
t
16
Positive clock edge to start of valid data 0.25 + T
LLC
/4 ns
t
17
Negative clock edge to end of valid data −2.95 + T
LLC
/4 ns
t
18
Negative clock edge to start of valid data −0.5 + T
LLC
/4 ns
1
Guaranteed by characterization.
2
TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.
3
SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
4
CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.
5
DDR timing specifications dependent on LLC output pixel clock; T
LLC
/4 = 9.25 ns at LLC = 27 MHz.
Timing Diagrams
SDATA
SCLK
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
t
3
09994-002
Figure 2. I
2
C Timing
