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ADV7181DWBCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet ADV7181D
Rev. A | Page 15 of 24
ANALOG INPUT MUXING
The ADV7181D has an integrated analog muxing section, which allows more than one source of video signal to be connected to the
decoder. Figure 7 outlines the overall structure of the input muxing provided in the ADV7181D.
ADC2_SW[3:0]
ADC3_SW[3:0]
A
IN
3
A
IN
6
A
IN
7
A
IN
8
A
IN
9
A
IN
10
A
IN
1
A
IN
6
ADC1_SW[3:0]
A
IN
5
A
IN
6
A
IN
4
A
IN
7
A
IN
8
A
IN
9
A
IN
10
ADC0_SW[3:0]
ADC_SW_MAN_EN
A
IN
5
A
IN
6
A
IN
4
A
IN
7
A
IN
2
A
IN
3
A
IN
1
A
IN
8
A
IN
9
A
IN
10
A
IN
5
A
IN
6
A
IN
4
A
IN
7
A
IN
2
A
IN
3
A
IN
1
A
IN
8
A
IN
9
A
IN
10
ADC2
ADC3
ADC1
ADC0
1
1
1
1
09994-007
Figure 7. Internal Pin Connections
ADV7181D Data Sheet
Rev. A | Page 16 of 24
Table 8 provides the recommended ADC mapping for the ADV7181D.
Table 8. Recommended ADC Mapping
Mode Required ADC Mapping Analog Input Channel Core Configuration
1
CVBS ADC0 CVBS = A
IN
1 SDP INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
YC/YC Auto Y = ADC0
C = ADC1
Y = A
IN
7
C = A
IN
9
SDP INSEL[3:0] = 0000
SDM_SEL[1:0] = 11
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
Component YUV Y = ADC0
U = ADC2
V = ADC1
Y = A
IN
10
U = A
IN
8
V = A
IN
6
SDP INSEL[3:0] = 1001
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
Component YUV Y = ADC0
U = ADC2
V = ADC1
Y = A
IN
10
U = A
IN
8
V = A
IN
6
CP INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 1010
SCART RGB CBVS = ADC0
G = ADC1
B = ADC3
R = ADC2
CVBS = A
IN
4
G = A
IN
10
B = A
IN
6
R = A
IN
8
SDP INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
Graphics
RGB Mode
G = ADC0
B = ADC2
R = ADC1
G = A
IN
2
B = A
IN
3
R = A
IN
5
CP INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0010
VID_STD[3:0] = 1100
1
Configuration to format follow-on blocks in correct frame.
Data Sheet ADV7181D
Rev. A | Page 17 of 24
The analog input muxes of the ADV7181D must be controlled
directly. This is referred to as manual input muxing. The manual
muxing is activated by setting the ADC_SW_MAN_EN bit (see
Table 9 ). It affects only the analog switches in front of the ADCs.
The INSEL, SDM_SEL, PRIM_MODE, and VID_STD bits must
still be set so that the follow-on blocks process the video data in
the correct format.
Not every input pin can be routed to any ADC. The analog
signal routing inside the IC imposes restrictions on the channel
routing. See Table 9 for an overview of the routing capabilities
inside the chip. The four mux sections can be controlled by the
reserved control signal buses ADC0_SW[3:0], ADC1_SW[3:0],
ADC2_SW[3:0], and ADC3_SW[3:0].
Table 9 explains the ADC mapping configuration for the following:
• ADC_SW_MAN_EN, manual input muxing enable,
IO map, Address C4[7]
• ADC0_SW[3:0], ADC0 mux configuration, IO map,
Address C3[3:0]
• ADC1_SW[3:0], ADC1 mux configuration, IO map,
Address C3[7:4]
• ADC2_SW[3:0], ADC2 mux configuration, IO map,
Address C4[3:0]
• ADC3_SW[3:0], ADC3 mux configuration, IO map,
Address F3[7:4]
Table 9. Manual MUX Settings for All ADCs
ADC_SW_MAN_EN = 1
ADC0_SW[3:0]
ADC0
Connection
ADC1_SW[3:0]
ADC1
Connection
ADC2_SW[3:0]
ADC2
Connection
ADC3_SW[3:0]
ADC3
Connection
0000 N/A 0000 N/A 0000 N/A 0000 N/A
0001 A
IN
2 0001 N/A 0001 N/A 0001 N/A
0010 A
IN
3 0010 N/A 0010 A
IN
3 0010 N/A
0011 A
IN
5 0011 A
IN
5 0011 N/A 0011 N/A
0100 A
IN
6 0100 A
IN
6 0100 A
IN
6 0100 A
IN
6
0101 A
IN
8 0101 A
IN
8 0101 A
IN
8 0101 N/A
0110 A
IN
10 0110 A
IN
10 0110 A
IN
10 0110 N/A
0111
N/A
0111
N/A
0111
N/A
0111
N/A
1000 N/A 1000 N/A 1000 N/A 1000 N/A
1001 A
IN
1 1001 N/A 1001 N/A 1001 A
IN
1
1010 N/A 1010 N/A 1010 N/A 1010 N/A
1011 A
IN
4 1011 A
IN
4 1011 N/A 1011 N/A
1100 N/A 1100 N/A 1100 N/A 1100 N/A
1101 A
IN
7 1101 A
IN
7 1101 A
IN
7 1101 N/A
1110 A
IN
9 1110 A
IN
9 1110 A
IN
9 1110 N/A
1111 N/A 1111 N/A 1111 N/A 1111 N/A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ADV7181DWBCPZ

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Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD/HD Video Decoder
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