Data Sheet ADV7181D
Rev. A | Page 3 of 24
FUNCTIONAL BLOCK DIAGRAM
INPUT
MUX
DATA
PREPROCESSOR
DECIMATION
AND
DOWNSAMPLING
FILTERS
STANDARD DEFINITION PROCESSOR
LUMA
FILTER
OUTPUT FIFO AND FORMATTER
A
IN
1
TO
A
IN
10
ADV7181D
SERIAL INTERFACE
CONTROL AND VBI DATA
SCLK
SDATA
ALSB
SYNC
EXTRACT
20
HS/CS
10
10
PIXEL
DATA
P19 TO
P10
P9 TO
P0
VS
FIELD/DE
LLC
SFL/
SYNC_OUT
CVBS
S-VIDEO
YPrPb
SCART–
(RGB + CVBS)
GRAPHICS RGB
10
CHROMA
FILTER
CHROMA
DEMOD
f
SC
RECOVERY
INT
LUMA
RESAMPLE
LUMA
2D COMB
(5H MAX)
RESAMPLE
CONTROL
CHROMA
RESAMPLE
CHROMA
2D COMB
(4H MAX)
FAST
BLANK
OVERLAY
CONTROL
AND
AV CODE
INSERTION
FB
Y
Cb
Cr
VBI DATA RECOVERY
MACROVISION
DETECTION
STANDARD
AUTODETECTION
CVBS/Y
C
Cb
Cr
FB
Cb
Y
COLOR SPACE
CONVERSION
CVBS
Cr
COMPONENT PROCESSOR
SSPD
STDI
SYNC PROCESSING AND
CLOCK GENERATION
HS_IN/
CS_IN
VS_IN
SOG
SOY
XTAL XTAL1
DIGITAL
FINE
CLAMP
GAIN
CONTROL
OFFSET
CONTROL
AV CODE
INSERTION
20
10
10
10
10
10
10
10
ACTIVE PEAK
AND
AGC
MACROVISION
DETECTION
CGMS DATA
EXTRACTION
10
ADC0CLAMP
ANTI-
ALIASING
FILTER
10
ADC3CLAMP
10
ADC2CLAMP
10
ADC1CLAMP
09994-001
ANTI-
ALIASING
FILTER
ANTI-
ALIASING
FILTER
ANTI-
ALIASING
FILTER
Figure 1.
ADV7181D Data Sheet
Rev. A | Page 4 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range = 1.6 V. T
MIN
to T
MAX
= −40°C to +85°C, unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.
Table 1.
Parameter
1
Symbol Test Conditions/Comments Min Typ Max Unit
STATIC PERFORMANCE
2, 3
Resolution (Each ADC)
N
10
Bits
Integral Nonlinearity INL BSL at 27 MHz (10-bit level) ±0.6 ±2.5 LSB
BSL at 54 MHz (10-bit level) −0.6/+0.7 LSB
BSL at 74 MHz (10-bit level) ±1.4 LSB
Differential Nonlinearity DNL At 27 MHz (10-bit level) −0.2/+0.25 −0.99/+2.5 LSB
At 54 MHz (10-bit level) −0.2/+0.25 LSB
At 74 MHz (10-bit level) ±0.9 LSB
DIGITAL INPUTS
Input High Voltage
4
V
IH
2 V
HS_IN, VS_IN low trigger mode 0.7 V
Input Low Voltage
5
V
IL
0.8 V
HS_IN, VS_IN low trigger mode 0.3 V
Input Current I
IN
−10 +10 µA
Input Capacitance
6
C
IN
10 pF
DIGITAL OUTPUTS
Output High Voltage
7
V
OH
I
= 0.4 mA 2.4 V
Output Low Voltage
7
V
OL
I
= 3.2 mA 0.4 V
High Impedance Leakage Current I
LEAK
Pin 1 60 µA
All other output pins 10 µA
Output Capacitance
6
C
OUT
20 pF
POWER REQUIREMENTS
6
Digital Core Power Supply DVDD 1.65 1.8 2.0 V
Digital I/O Power Supply DVDDIO 3.0 3.3 3.6 V
PLL Power Supply PVDD 1.71 1.8 1.89 V
Analog Power Supply AVDD 3.15 3.3 3.45 V
Digital Core Supply Current
I
DVDD
105
mA
Graphics RGB sampling at 75 MHz 90 mA
SCART RGB FB sampling at 54 MHz 106 mA
Digital I/O Supply Current I
DVDDIO
CVBS input sampling at 54 MHz 4 mA
Graphics RGB sampling at 75 MHz 38 mA
PLL Supply Current I
PVDD
CVBS input sampling at 54 MHz 11 mA
Graphics RGB sampling at 75 MHz 12 mA
Analog Supply Current
8
I
AVDD
CVBS input sampling at 54 MHz 99 mA
Graphics RGB sampling at 75 MHz 166 mA
SCART RGB FB sampling at 54 MHz 200 mA
Power-Down Current I
PWRDN
2.25 mA
Green Mode Power-Down I
PWRDNG
Synchronization bypass function 16 mA
Power-Up Time
t
PWRUP
20
ms
1
All specifications are obtained using the Analog Devices, Inc., recommended programming scripts.
2
All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%.
3
Maximum INL and DNL specifications obtained with part configured for component video input.
4
To obtain specified V
IH
level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then V
IH
on Pin 22 is 1.2 V.
5
To obtain specified V
IL
level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then V
IL
on Pin 22 is 0.4 V.
6
Guaranteed by characterization.
7
V
OH
and V
OL
levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
8
For CVBS current measurements only, ADC0 is powered up. For RGB current measurements only, ADC0, ADC1, and ADC2 are powered up. For SCART FB current
measurements, all four ADCs are powered up.
Data Sheet ADV7181D
Rev. A | Page 5 of 24
VIDEO SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T
MIN
to T
MAX
= −40°C to +85°C,
unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.
Table 2.
Parameter
1
Symbol Test Conditions/Comments Min Typ Max Unit
NONLINEAR SPECIFICATIONS
Differential Phase DP CVBS input, modulated 5 step 0.5 Degrees
Differential Gain DG CVBS input, modulated 5 step 0.5 %
Luma Nonlinearity LNL CVBS input, 5 step 0.5 %
NOISE SPECIFICATIONS
Signal-to-Noise Ratio, Unweighted SNR Luma ramp 54 56 dB
Luma flat field 58 60 dB
Analog Front-End Crosstalk
60
dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range −5 +5 %
Vertical Lock Range 40 70 Hz
f
SC
Subcarrier Lock Range ±1.3 kHz
Color Lock-In Time 60 Lines
Synchronization Depth Range
2
20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 Fields
Horizontal Lock Time 100 Lines
CHROMA SPECIFICATIONS
Hue Accuracy
1
Degrees
Color Saturation Accuracy CL_AC 1 %
Color AGC Range 5 400 %
Chroma Amplitude Error 0.5 %
Chroma Phase Error 0.4 Degrees
Chroma Luma Intermodulation 0.2 %
LUMA SPECIFICATIONS
Luma Brightness Accuracy CVBS, 1 V input 1 %
Luma Contrast Accuracy CVBS, 1 V input 1 %
1
Guaranteed by characterization.
2
Nominal synchronization depth is 300 mV at 100% synchronization depth range.

ADV7181DWBCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD/HD Video Decoder
Lifecycle:
New from this manufacturer.
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