ADV7181D Data Sheet
Rev. A | Page 18 of 24
PIXEL OUTPUT FORMATTING
Table 10. SDP Output Formats—SDR 4:2:2 (8-/10-/16-/20-Bit)
Pixel Output Pin
8-Bit SDR
ITU-R BT.656
10-Bit SDR
ITU-R BT.656 16-Bit SDR 20-Bit SDR
P19 Y7, Cb7, Cr7 Y9, Cb9, Cr9 Y7 Y9
P18 Y6, Cb6, Cr6 Y8, Cb8, Cr8 Y6 Y8
P17 Y5, Cb5, Cr5 Y7, Cb7, Cr7 Y5 Y7
P16 Y4, Cb4, Cr4 Y6, Cb6, Cr6 Y4 Y6
P15 Y3, Cb3, Cr3 Y5, Cb5, Cr5 Y3 Y5
P13 Y1, Cb1, Cr1 Y3, Cb3, Cr3 Y1 Y3
P12 Y0, Cb0, Cr0 Y2, Cb2, Cr2 Y0 Y2
P11 High-Z Y1, Cb1, Cr1 High-Z Y1
P10 High-Z Y0, Cb0, Cr0 High-Z Y0
P9 High-Z High-Z Cb7, Cr7 Cb9, Cr9
P8 High-Z High-Z Cb6, Cr6 Cb8, Cr8
P7 High-Z High-Z Cb5, Cr5 Cb7, Cr7
P6 High-Z High-Z Cb4, Cr4 Cb6, Cr6
P5 High-Z High-Z Cb3, Cr3 Cb5, Cr5
P4 High-Z High-Z Cb2, Cr2 Cb4, Cr4
P2 High-Z High-Z Cb0, Cr0 Cb2, Cr2
P1 High-Z High-Z High-Z Cb1, Cr1
P0 High-Z High-Z High-Z Cb0, Cr0
Table 11. CP Output Formats—SDR 4:2:2 (16-/20-Bit) and DDR 4:4:4 (12-Bit)
Pixel Output
SDR 4:2:2 12-Bit DDR 4:4:4
1
16-Bit SDR 20-Bit SDR Clock Rise Clock Fall
P19 Y7 Y9 B7-0 R3-1
P18 Y6 Y8 B6-0 R2-1
P16 Y4 Y6 B4-0 R0-1
P15 Y3 Y5 B3-0 G7-1
P14 Y2 Y4 B2-0 G6-1
P13 Y1 Y3 B1-0 G5-1
P12 Y0 Y2 B0-0 G4-1
P11 High-Z Y1 High-Z High-Z
P10 High-Z Y0 High-Z High-Z
P9 Cb7, Cr7 Cb9, Cr9 G3-0 R7-1
P8 Cb6, Cr6 Cb8, Cr8 G2-0 R6-1
P7 Cb5, Cr5 Cb7, Cr7 G1-0 R5-1
P6 Cb4, Cr4 Cb6, Cr6 G0-0 R4-1
P5 Cb3, Cr3 Cb5, Cr5 High-Z High-Z
P4 Cb2, Cr2 Cb4, Cr4 High-Z High-Z
P3 Cb1, Cr1 Cb3, Cr3 High-Z High-Z
P2 Cb0, Cr0 Cb2, Cr2 High-Z High-Z
P1 High-Z Cb1, Cr1 High-Z High-Z
1
xx-0 corresponds to data clocked at the rising edge; xx-1 corresponds to data clocked at the falling edge.
