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7133LA45J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy".
2. t
BDD is calculated parameter and is greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual).
3. To ensure that the earlier of the two ports wins.
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (SA or LA).
7133X20
7143X20
Com'l Only
7133X25
7143X25
Com'l & Ind
7133X35
7143X35
Com'l
& Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER 71V33)
t
BAA
BUSY Access Time from Address
____
20
____
20
____
30 ns
t
BDA
BUSY Disable Time from Address
____
20
____
20
____
30 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
20
____
25 ns
t
BDC
BUSY Disable Time from Chip Enable
____
17
____
20
____
25 ns
t
WDD
Write Pulse to Data Delay
(1)
____
40
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
30
____
35
____
45 ns
t
BDD
BUSY Disable to Valid Data
(2)
____
25
____
30
____
35 ns
t
APS
Arbitration Priority Set-up Time
(3)
5
____
5
____
5
____
ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
25
____
ns
BUSY INPUT TIMING (For SLAVE 71V43)
t
WB
BUSY Inp ut to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
25
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
40
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
30
____
35
____
45 ns
2746 tbl 12a
7133X45
7143X45
Com'l Only
7133X55
7143X55
Com'l, Ind
& Military
7133X70/90
7143X70/90
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER 71V33)
t
BAA
BUSY Access Time from Address
____
40
____
40
____
45/45 ns
t
BDA
BUSY Disable Time from Address
____
40
____
40
____
45/45 ns
t
BAC
BUSY Access Time from Chip Enable
____
30
____
35
____
35/35 ns
t
BDC
BUSY Disable Time from Chip Enable
____
25
____
30
____
30/30 ns
t
WDD
Write Pulse to Data Delay
(1)
____
80
____
80
____
90/90 ns
t
DDD
Write Data Valid to Read Data De lay
(1)
____
55
____
55
____
70/70 ns
t
BDD
BUSY Disable to Valid Data
(2)
____
40
____
40
____
40/40 ns
t
APS
Arbitration Priority Se t-up Time
(3)
5
____
5
____
5/5
____
ns
t
WH
Write Hold After BUSY
(5)
30
____
30
____
30/30
____
ns
BUSY INPUT TIMING (For SLAVE 71V43)
t
WB
BUSY Inp ut to Write
(4)
0
____
0
____
0/0
____
ns
t
WH
Write Hold After BUSY
(5)
30
____
30
____
30/30
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
80
____
80
____
90/90 ns
t
DDD
Write Data Valid to Read Data De lay
(1)
____
55
____
55
____
70/70 ns
2746 tbl 12b
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges
11
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a CE = VIL and a R/W = VIL.
3. t
WR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. Timing depends on which enable signal is de-asserted first, CE or OE.
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required t
DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP.
9. R/W for either upper or lower byte.
Write Cycle No. 2 (CE Controlled Timing)
(1,5)
Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing)
(1,5,8)
CE
2746 drw 09
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/W
t
WP
t
DH
DATA
OUT
t
WZ
(7)
(4)
(2)
t
OW
OE
(9)
t
LZ
(7)
t
HZ
(6)
(3)
(4)
(7)
t
HZ
CE
2746 drw 10
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/W
t
EW
t
DH
(9)
(6)
(2)
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges
12
2746 drw 11
t
DW
t
APS
ADDR
"A"
t
WC
MATCH
t
WP
R/W
"A"
DATA
IN"A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(4)
t
WDD
DATA
OUT "B"
Timing Waveform of Write with Port-to-Port Read and BUSY
(1,2,3)
Timing Waveform of Write with BUSY
(3)
NOTES:
1. t
WH must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master).
2. BUSY is asserted on port "B" blocking R/W
"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "
A" may be either left or right port. Port "B" is the opposite from port "A".
NOTES:
1. To ensure that the earlier of the two ports wins, t
APS is ignored for Slave (IDT7143).
2. CE
L = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2746 drw 12
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
,
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

7133LA45J

Mfr. #:
Buy 7133LA45J
Manufacturer:
IDT
Description:
SRAM 32K(2KX16)CMOS DUALPORT R
Lifecycle:
New from this manufacturer.
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