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MAX9258GCM/V+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
parity encoding that adds two parity bits to the serial
word. Bit 0 (EN0) is the LSB that is serialized first with-
out parity enabled. The parity bits are serialized first
when parity is enabled.
The ECU programs the MAX9258, MAX9257, and
peripheral devices at startup and during the control
channel phase. In a digital video system, the control
channel phase occurs during the vertical blanking time
and synchronizes to the VSYNC signal. The programma-
ble active edge of VSYNC initiates the control channel
phase. Nonactive edge of VSYNC can transition at any
time after 8 x t
T
if MAX9257 spread is not enabled and
0.5/f
SSM
when enabled. At the end of video phase, the
MAX9258 drives CCEN high to indicate to the ECU that
the control channel is open. Programmable timers and
ECU signal activity determine how long the control
channel stays open. The timers are reset by ECU signal
activity. ECU programming must not exceed the vertical
blanking time to avoid loss of video data.
After the control channel phase closes, the MAX9257
sends a 546 or 1090 word pattern as handshaking
(HSK) to synchronize the MAX9258’s internal clock
recovery circuit to the MAX9257’s transmitted data.
Following the handshaking, the control channel is
closed and the video phase begins. The serial LVDS
data is recovered and parallel data is valid on the pro-
grammed edge of the recovered pixel clock.
MAX9257/MAX9258
______________________________________________________________________________________ 19
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
VIDEO
VIDEO
HSK
CONTROL
VSYNC_IN
SDI/O±
SDI/O±
CCEN
HSK = HANDSHAKING
0.5/f
SSM
(max)
SPREAD
PROFILE
Figure 20. Video and Control Channel Phases (MAX9257 Spread is Enabled)
VIDEO
VIDEO
HSK
CONTROL
VSYNC_IN
SDI/O±
SDI/O±
CCEN
HSK = HANDSHAKING
8t
T
Figure 19. Video and Control Channel Phases (Spread Off)
MAX9257/MAX9258
20 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
REGISTER NAME
REGISTER
ADDRESS (hex)
POWER-UP VALUE
(hex)
POWER-UP DEFAULT SETTINGS
REG0 0x00 0xB5
PRATE = 10, 20MHz to 40MHz
SRATE = 11, 400Mbps to 840Mbps
PAREN = 0, parity disabled
PWIDTH = 101, parallel data width = 18
REG1 0x01 0x1F
SPREAD = 000, spread = off
Reserved = 11111
REG2 0x02 0xA0
STODIV = 1010, STO clock is pixel clock divided by 1024
STOCNT = 0000, STO counter counts to 1
REG3 0x03 0xA0
ETODIV = 1010, ETO clock is pixel clock divided by 1024
ETOCNT = 0000, ETO counter counts to 1
REG4 0x04
1) REM = 0, 0x28
2) REM = 1, 0x30
VEDGE = 0, VSYNC active edge is falling
Reserved = 0
CKEDGE = 1, pixel clock active edge is rising
PD: 1) If REM = 0, PD = 0
2) If REM = 1, PD = 1
SEREN: 1) If REM = 0, SEREN = 1
2) If REM = 1, SEREN = 0
BYPFPLL = 0, filter PLL is active
Reserved = 0
PRBSEN = 0, PRBS test disabled
REG5 0x05 0xFA MAX9257 address = 1111 1010
REG6 0x06 0xFF End frame = 1111 1111
REG7 0x07 0xF8 MAX9258 address = 1111 1000
REG8 0x08 0x00
INTMODE = 0, interface with peripheral is UART
INTEN = 0, interface with peripheral is disabled
FAST = 0, UART bit rate = DC to 4.25Mbps
CTO = 000, never come back
BITRATE = 00, base mode bit rate = 95kbps to 400kbps
REG9 0x09 0x00
PRBSLEN = 0000, PRBS word length = 2
21
GPIO9DIR = 0, GPIO9 = input
GPIO8DIR = 0, GPIO8 = input
GPIO9 = 0
GPIO8 = 0
REG10 0x0A 0x00
GPIO7DIR = 0, GPIO7 = input
GPIO6DIR = 0, GPIO6 = input
GPIO5DIR = 0, GPIO5 = input
GPIO4DIR = 0, GPIO4 = input
GPIO3DIR = 0, GPIO3 = input
GPIO2DIR = 0, GPIO2 = input
GPIO1DIR = 0, GPIO1 = input
GPIO0DIR = 0, GPIO0 = input
Table 1. MAX9257 Power-Up Default Register Map (see the
MAX9257 Register Table
)
MAX9257/MAX9258
______________________________________________________________________________________ 21
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
REGISTER NAME
REGISTER
ADDRESS (hex)
POWER-UP VALUE
(hex)
POWER-UP DEFAULT SETTINGS
REG11 0x0B 0x00
GPIO7 = 0
GPIO6 = 0
GPIO5 = 0
GPIO4 = 0
GPIO3 = 0
GPIO2 = 0
GPIO1 = 0
GPIO0 = 0
REG12 0x0C 0xE0
PREEMP = 111, preemphasis = 0%
Reserved = 00000
REG13 0x0D 0x00
Reserved = 000000
I2CFILT = 00, I
2
C glitch filter settings:
1) 95kbps to 400kbps = 100ns
2) 400kbps to 1000kbps = 50ns
3) 1000kbps to 4250kbps = 10ns
REG14 0x0E 0x00
Reserved = 0000 000
LOCKED = read only
Table 1. MAX9257 Power-Up Default Register Map (continued)
REGISTER NAME
REGISTER
ADDRESS (hex)
POWER-UP VALUE
(hex)
POWER-UP DEFAULT SETTINGS
REG0 0x00 0xB5
PRATE = 10, 20MHz to 40MHz
SRATE = 11, 400Mbps to 840Mbps
PAREN = 0, parity disabled
PWIDTH = 101, parallel data width = 18
REG1 0x01 0x00
SPREAD = 00, spread spectrum = off
AER = 0, error count is reset by reading error registers
Reserved = 0 0000
REG2 0x02 0xA0
STODIV = 1010, STO clock is pixel clock divided by 1024
STOCNT = 0000, STO counter counts to 1
REG3 0x03 0xA0
ETODIV = 1010, ETO clock is pixel clock divided by 1024
ETOCNT = 0000, ETO counter counts to 1
REG4 0x04 0x20
VEDGE = 0, VSYNC active edge is falling
HEDGE = 0, HSYNC active edge is falling
CKEDGE = 1, pixel clock active edge is rising
Reserved = 0000
PRBSEN = 0, PRBS test disabled
REG5 0x05 0xF8 MAX9258 address = 1111 1000
REG6 0x06 0xFF End frame = 1111 1111
REG7 0x07 0x00
INTMODE = 0, interface with peripheral is UART
INTEN = 0, interface with peripheral is disabled
FAST = 0, UART bit rate = DC to 4.25Mbps
CTO = 000, never come back
BITRATE = 00, base mode bit rate = 95kbps to 400kbps
Table 2. MAX9258 Power-Up Default Register Map (see the
MAX9258 Register Table
)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

MAX9258GCM/V+

Mfr. #:
Buy MAX9258GCM/V+
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes Prog Serializer / Deserializer
Lifecycle:
New from this manufacturer.
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