MAX9257/MAX9258
40 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
ADDRESS BITS DEFAULT
NAME DESCRIPTION
7:6 10 PRATE
Pixel clock frequency range
00 = 5MHz to 10MHz
01 = 10MHz to 20MHz
10 = 20MHz to 40MHz (default)
11 = 40MHz to 70MHz
5:4 11 SRATE
Serial-data rate range
00 = 60Mbps to 100Mbps
01 = 100Mbps to 200Mbps
10 = 200Mbps to 400Mbps
11 = 400Mbps to 840Mbps (default)
3 0 PAREN Parity enable 0 = disabled (default), 1 = enabled
0
2:0 101 PWIDTH
Parallel data width
(includes HSYNC and VSYNC, excludes DCB, INV, and parity bits)
000 = 10 100 = 18
001 = 12 101 = 18 (default)
010 = 14 110 = 18
011 = 16 111 = 18
7:5 000 SPREAD
Spread-spectrum setting
For PRATE ranges 00, 01: all spread options possible
For PRATE ranges 10, 11: maximum spread is 2%
000 = Off (default) 100 = Off
001 = 1.5% 101 = 3%
010 = 1.75% 110 = 3.5%
011 = 2% 111 = 4%
1
4:0 11111 Reserved (set to 11111)
Control channel start timeout: (STO) times out if ECU does not start using control channel within this amount of time
after control channel session is enabled.
7:4 1010 STODIV
Control channel start timeout divider
Pixel clock is first divided by:
0000 = 16 1000 = 256
0001 = 16 1001 = 512
0010 = 16 1010 = 1024 (default)
0011 = 16 1011 = 2048
0100 = 16 1100 = 4096
0101 = 32 1101 = 8192
0110 = 64 1110 = 16,384
0111 = 128 1111 = 32,768
2
3:0 0000 STOCNT
Control channel start timeout counter
Divided pixel clock is used to count up to (STOCNT + 1)
MAX9257 Register Table
Choosing I
2
C Pullup Resistors
I
2
C requires pullup resistors to provide a logic-high level
to data and clock lines. There are tradeoffs between
power dissipation and speed, and a compromise must
be made in choosing pullup resistor values. Every device
connected to the bus introduces some capacitance even
when device is not in operation. I
2
C specifies 300ns rise
times to go from low to high (30% to 70%) for fast mode,
which is defined for a date rate up to 400kbps (see I
2
C
specifications for details). To meet the rise time require-
ment, choose the pullup resistors so the rise time
t
R
= 0.85R
PULLUP
x C
BUS
< 300ns. If the transition time
becomes too slow, the setup and hold times may not be
met and waveforms will not be recognized.
MAX9257/MAX9258
______________________________________________________________________________________ 41
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
ADDRESS BITS DEFAULT
NAME DESCRIPTION
Control channel end timeout: (ETO) times out if ECU does not use control channel for this amount of time after it has
already used at least once.
7:4 1010 ETODIV
Control channel end timeout divider
Pixel clock is first divided by:
0000 = 16 1000 = 256
0001 = 16 1001 = 512
0010 = 16 1010 = 1024 (default)
0011 = 16 1011 = 2048
0100 = 16 1100 = 4096
0101 = 32 1101 = 8192
0110 = 64 1110 = 16,384
0111 = 128 1111 = 32,768
3
3:0 0000 ETOCNT
Control channel end timeout counter
Divided pixel clock is used to count up to (ETOCNT + 1)
7 0 VEDGE
VSYNC active edge at camera interface
0 = falling (default), 1 = rising
6 0 Reserved (set to 0)
5 1 CKEDGE
PCLK active edge at camera interface
0 = falling, 1 = rising (default)
40 PD
Power mode
0 = power-up, 1 = power-down
(when REM = 1 default is 1)
3 1 SEREN
Serialization enable
0 = disabled, 1 = enabled
(when REM = 1 default is 0)
2 0 BYPFPLL
Bypass filter PLL
0 = active (default), 1 = bypass
1 0 Reserved (set to 0)
4
0 0 PRBSEN
PRBS test enable
0 = disabled (default), 1 = enabled
7:1
1111101
DEVICEID 7-bit address of MAX9257
5
0 0 Reserved (set to 0)
7:1
1111111
EF End frame to close control channel
6
0 1 Reserved (set to 1)
7:1
1111100
DESID 7-bit address ID of MAX9258
7
0 0 Reserved (set to 0)
MAX9257 Register Table (continued)
MAX9257/MAX9258
42 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
ADDRESS BITS DEFAULT
NAME DESCRIPTION
7 0 INTMODE
Interface mode
0 = UART (default), 1 = I
2
C
6 0 INTEN
Interface enable
0 = disabled (default), 1 = enabled
5 0 FAST
Fast UART transceiver
0 = b i t r ate = D C to 4.25M b p s ( d efaul t) , 1 = b i t r ate = 4.25M b p s to 10M b p s
4:2 000 CTO
Timer to come back from bypass mode (in bit time)
000 = never come back (default) 100 = 64
001 = 16 101 = 80
010 = 32 110 = 96
011 = 48 111 = 112
8
1:0 00 BITRATE
Control channel bit rate range in base mode
00 = 95kbps to 400kbps (default)
01 = 400kbps to 1000kbps
10 = 1000kbps to 4250kbps
11 = 1000kbps to 4250kbps
7:4 0000 PRBSLEN
PRBS test number of words
1111 = continuous else = 2
(PRBSLEN + 21)
3 0 GPIO9DIR GPIO 9 direction 0 = input (default), 1 = output
2 0 GPIO8DIR GPIO 8 direction 0 = input (default), 1 = output
1 0 GPIO9* General purpose input output 9
9
0 0 GPIO8* General purpose input output 8
7 0 GPIO7DIR GPIO 7 direction 0 = input (default), 1 = output
6 0 GPIO6DIR GPIO 6 direction 0 = input (default), 1 = output
5 0 GPIO5DIR GPIO 5 direction 0 = input (default), 1 = output
4 0 GPIO4DIR GPIO 4 direction 0 = input (default), 1 = output
3 0 GPIO3DIR GPIO 3 direction 0 = input (default), 1 = output
2 0 GPIO2DIR GPIO 2 direction 0 = input (default), 1 = output
1 0 GPIO1DIR GPIO 1 direction 0 = input (default), 1 = output
10
0 0 GPIO0DIR GPIO 0 direction 0 = input (default), 1 = output
7 0 GPIO7* General purpose input output 7
6 0 GPIO6* General purpose input output 6
5 0 GPIO5* General purpose input output 5
4 0 GPIO4* General purpose input output 4
3 0 GPIO3* General purpose input output 3
2 0 GPIO2* General purpose input output 2
1 0 GPIO1* General purpose input output 1
11
0 0 GPIO0* General purpose input output 0
MAX9257 Register Table (continued)

MAX9258GCM/V+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes Prog Serializer / Deserializer
Lifecycle:
New from this manufacturer.
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