MAX9258GCM/V+ Datasheet MAX9258GCM/V+, MAX9257GTL+T, MAX9257GTL/V+ | P31-P33

Assuming a UART bit rate of 2Mbps, REG2[7:4],

REG3[7:4] = 100 (Table 26), CTO = 64, CTO timeout

calculated as:

CTO

= (0.5µs) × 64 = 32µs

Link Power-Up

The MAX9258 powers up when the power-down input

PD goes high. After approximately 130µs, CCEN goes

high, indicating the control channel is available. This

delay is required because the analog circuitry has to

fully wake up. There are two ways to power up the

MAX9257. The MAX9257 powers up according to the

state of REM. ECU powers up MAX9257 remotely (ECU

sends command to power up) when REM is pulled to

. The MAX9257 powers up according to the supply

voltage when REM is grounded.

Powering the MAX9257 with Serialization Enabled

(REM = Ground at Power-Up)

When REM is grounded, the MAX9257 fully powers up

when power is applied. The power-down bit PD

(REG4[4]) is disabled and serialization bit SEREN

(REG4[3]) is enabled. If PCLK_IN is not running, the

MAX9257 stays in the control channel. After PCLK_IN is

applied, the control channel times out due to STO, ETO,

or EF. The MAX9257 starts the handshaking after the

MAX9257 locks to PCLK after 32,768 clock cycles. If

PCLK_IN is running, serialization starts automatically

after PLL of the MAX9257 locks to PCLK_IN with default

values in the registers.

Remote Power-Up of the MAX9257

(REM = Pulled Up to V

)

When REM is pulled up to V

, the MAX9257 wakes up

in a low power state, drawing less than 100µA supply

current. To wake-up the MAX9257, the ECU first trans-

mits a dummy frame 0xDB and then waits at least

100µs to allow the MAX9257’s internal analog circuitry

to fully power up. Then the ECU configures the

MAX9257 registers, including a write to disable the PD

bit (REG4[4]) so that the MAX9257 does not return

back to the low power state. Every packet needs to

start with a synchronization frame (see the

UART

sec-

tion). If the PD bit is not disabled within 70ms after

transmitting the dummy frame, the MAX9257 returns to

the low power state and the whole power-up sequence

needs to be repeated. After configuration is complete,

the ECU also needs to enable the SEREN bit to start the

video phase.

At initial power-up with REM pulled to V

, default value

of SEREN bit is 0, so STO and ETO timers are not active.

Control channel is enabled as long as SEREN is 0.

This allows the control channel to be used for extensive

programming at initial power-up without the channel

timing out. UART, parity, framing and packet errors in

the control channel communications are reported if end

frame is used to close control channel (see the

MAX9258 Error Checking and Reporting

section). For

faster identification of errors, verify every write com-

mand by reading back the registers before enabling

serialization.

Link Power-Down

When the control channel is open, the ECU writes to the

PD bit to power down the MAX9257. In this case, to

power up the MAX9257 again, the power-up sequence

explained in the

Remote Power-Up of the MAX9257 (REM

= Pulled Up to V

)

section needs to be repeated. The

MAX9258 has a PD input that powers down the device.

MAX9258 Error Checking and Reporting

The MAX9258 has an open-drain ERROR output. This

output indicates various error conditions encountered

during the operation of the system. When an error con-

dition is detected and needs to be reported, ERROR

asserts low. ERROR indicates three error conditions:

UART, video parity, and PRBS errors.

UART Errors

During control channel communication in base mode,

the MAX9257/MAX9258 record UART frame, parity, and

packet errors. I

C errors are also recorded by

MAX9257 when I

C interface is enabled. If ECU closes

the control channel by using end frame (EF), the

MAX9257 sends a special internal UART frame back to

the MAX9258 called error frame. The MAX9257 UART

and I

C errors are reset at the next control channel. The

MAX9258 receives the error frame and records the

error status in its UART error register (REG13). ECU

must use end frame to the close control channel for the

MAX9257 to report back UART and I

C errors to the

MAX9258. Whenever one of the bits in the UART error

ter is reset when ECU reads it, and ERROR deasserts

high immediately if UART errors were the only reason

that ERROR was asserted low. If the MAX9258 is not

locked (LOCK = low), UART error is not reported.

Video Parity Errors

When video parity check is enabled (REG0[3] in both

devices), the MAX9258 counts the number of video pari-

ty errors by checking recovered video words. Value of

this counter is reflected in PAERRHI (8 MSB bits,

REG11) and PAERRLO (8 LSB bits, REG10). If the num-

ber of detected parity errors is greater than or equal to

the parity error threshold PATHRHI (REG9) and

PATHRLO (REG8), then ERROR asserts low. In this

MAX9257/MAX9258

______________________________________________________________________________________ 31

Fully Programmable Serializer/Deserializer

with UART/I

C Control Channel

MAX9257/MAX9258

case, ERROR deasserts high after next video phase

starts if video parity errors were the only reason that

ERROR was asserted low. To report parity errors in

bypass mode, program autoerror reset (AER) to 1

(REG1[5] = 1).

Autoerror Reset

The default method to reset errors is to read the respec-

tive error registers in the MAX9258 (registers 10, 11, and

13). If errors were present before the next control chan-

nel, the error count gets incremented to the previous

number. By setting the autoerror reset (AER) bit to 1, the

error registers reset when the control channel ends.

Setting AER to 1 does not reset PRBS errors.

PRBS Errors

During the PRBS test, the MAX9258 checks received

PRBS data words by comparing them to internally gener-

ated PRBS data. Detected errors are counted in the PRBS

error register (REG12) in the MAX9258. Whenever the

number of detected PRBS errors is more than 0, ERROR

asserts low. The PRBS error register is reset when ECU

writes a 0 to PRBSEN register (REG4[0]). In this case,

ERROR deasserts high immediately if PRBS errors were

the only reason that ERROR was asserted low.

Short Synchronization Pattern

The short synchronization pattern is part of the handshak-

ing procedure between the MAX9257 and MAX9258 after

the control channel phase. It is used to resynchronize the

MAX9258’s clock and data recovery circuit to the

MAX9257 before the video phase begins. The MAX9257

transmits the short synchronization pattern when it

receives the lock frame from the MAX9258. The length of

short synchronization pattern is dependant on the PRATE

range. When PRATE is 00 or 01, the short synchroniza-

tion pattern consists of 546 words and when PRATE is 10

or 11, the short synchronization pattern consists of 1090

words. Every word is one pixel clock period.

Long Synchronization Pattern

At power-up or when the MAX9257 does not receive a

lock frame from the MAX9258, the MAX9257 transmits a

long synchronization pattern. The long synchronization

pattern consists of 17,410 words. Every word is one

pixel clock period. When REM is high, if synchroniza-

tion is not achieved after 62 attempts, the MAX9257

resets SEREN to 0 so that the control channel stays

open to allow troubleshooting. When REM is low, the

MAX9257/MAX9258 continuously tries to reestablish the

connection.

Lock Verification (Handshaking)

At the end of every vertical blanking time, the MAX9257

verifies that the MAX9258 did not lose lock. The

MAX9258 handshakes with the MAX9257 to indicate

lock status. The handshaking occurs after the channel

closes (Figures 22 and 23). If the number of decoding

errors in a time window did not exceed a certain thresh-

old during the last video phase, the MAX9258 sends

back the lock frame that indicates lock. If the MAX9257

receives the lock frame, the MAX9257 transmits a short

synchronization pattern. The MAX9258 features a pro-

prietary VCO mechanism that prevents frequency drift

while in the control channel. This allows for successful

resynchronization after extended use of control chan-

nel. If the number of decoding errors in a time window

exceeds a certain threshold, the MAX9258 loses lock,

LOCK goes low, and the lock frame is not sent. The

MAX9258 also loses lock if handshaking is not suc-

cessful. If the MAX9257 does not receive the lock

frame, it transmits a long synchronization pattern before

the start of next video phase. When REM = 1, if the lock

frame is not received by the MAX9257 after 62 consec-

utive attempts to synchronize, SEREN is disabled so

that the control channel opens permanently for trou-

bleshooting.

Link Status (LOCK and CCEN)

The LOCK output indicates whether the MAX9258 is

locked to the MAX9257. LOCK is an open-drain output

that needs to be pulled up to V

. LOCK asserts low to

indicate that the MAX9258 is not locked to the

MAX9257 and high when it is. In the control channel

phase, LOCK stays high if LOCK is high in the video

phase. While in the control channel phase, the

MAX9258 PLL frequency is held constant, PCLK output

is active and data outputs are frozen at their last valid

value before entering the control channel. CCEN output

indicates whether the MAX9257/MAX9258 are in the

control channel phase or video phase. CCEN goes high

when the MAX9257/MAX9258 are in the control channel

phase (Table 27). Only at initial power-up, CCEN goes

high before communication in the control channel is

ready (see the

Link Power-Up

section).

32 ______________________________________________________________________________________

Fully Programmable Serializer/Deserializer

with UART/I

C Control Channel

LOCK CCEN INDICATION

1 0 LVDS channel active

1 1 Control channel active

0 X PLL loss of lock

Table 27. Link Status

Control Channel

Overview of Control Channel Operation

The control channel is used by the ECU to program

registers in the MAX9257, MAX9258, and peripheral

devices (such as a camera) during vertical blanking,

after power-up, or when serialization is disabled.

Control channel communication is half-duplex UART.

The peripheral interface on the MAX9257 can be pro-

grammed to be I

C or UART. Operation of the control

channel is synchronized with the VSYNC input after the

ECU starts serialization of video data. Programmable

timers, ECU signal activity, and end frame determine

how long the control channel stays open. The control

channel remains open as long as there is signal activity

from the ECU. When the control channel closes, the

LVDS serial link is reestablished. Once serialization is

enabled, the programming of registers (including the

control channel overhead time) must be completed

within the vertical blanking time to avoid loss of video

data. VSYNC can deassert while control channel

remains open after eight pixel clock cycles.

The control channel phase begins on the transition of

the programmed active edge of VSYNC_IN. In video

applications, the VSYNC signal of the peripheral device

is connected to VSYNC_IN on the MAX9257. In other

applications, a different signal can be used to trigger

the control channel phase. When the MAX9257/

MAX9258 detect the VSYNC_IN transition, the LVDS

video phase disables and the control channel phase is

enabled.

The control channel operates in two modes: base and

bypass. In base mode, the ECU issues UART com-

mands in a specified format to program the

MAX9257/MAX9258 registers. GPIO on the MAX9257

are also programmed in base mode. UART commands

are translated to I

C and output to peripheral devices

connected to the MAX9257 when not addressed to

either the MAX9257 or the MAX9258.

In bypass mode, programming of the MAX9257/

MAX9258 registers are temporarily or permanently

blocked depending on the programmed value of CTO.

Blocking prevents unintentional programming of the

MAX9257/MAX9258 registers when the ECU communi-

cates with the peripheral using a UART protocol differ-

ent than the one specified to program the MAX9257/

MAX9258. When the control channel is open, the

MAX9258 continues outputting the pixel clock while

HSYNC and video data are held at the last value. If

spread is enabled on the MAX9258, the pixel clock is

spread.

Control Channel Overhead

Control channel overhead consists of lock frame, short

synchronization sequence, and error frame. The lock

frame is transmitted between the MAX9257 and the

MAX9258 without action by the ECU. The error frame is

only sent in response to end frame. When MAX9257

spread spectrum is enabled, the control channel is

entered after spread reaches center frequency. The over-

head from VSYNC falling edge to control channel enable

accounts for a maximum of 1400 pixel clock cycles.

Base Mode (Details)

Base mode allows the ECU to communicate with the

MAX9257/MAX9258 in UART and a peripheral device in

C. UART programming of the peripheral device is not

possible in base mode. UART packets from the ECU

need to follow a certain protocol to program the MAX9257

and the MAX9258 (Figures 28 and 29). Packets not

addressed to the MAX9257/MAX9258 get converted to

C by the MAX9257 and pass to the peripheral device.

The MAX9257 receives I

C packets from the peripheral

device and converts them to UART packets to send back

to the ECU. To disable communication to the peripheral

device, write a 0 to INTEN (REG8[6] in the MAX9257 and

REG7[6] in the MAX9258).

In base mode, the STO/ETO timers and the EF command

are used to control the duration of the control channel.

STO and ETO count up and expire when they reach their

programmed value. STO and ETO are not enabled at the

same time. STO is enabled after CCEN goes high. If there

is activity from the ECU before STO times out, STO is dis-

abled and ETO is enabled. The ECU must begin a trans-

action within an STO timeout or else the channel closes.

The ECU can close the channel by allowing ETO to time-

out. Activity from the ECU resets the ETO timer. Another

way to close the control channel is by sending an end

frame (EF). EF closes the channel within 2 to 3 bit times

after being received by the MAX9257/MAX9258. The

default value of EF is 0xFF, but can be programmed to

any other value besides the MAX9257 and the MAX9258

device addresses. The control channel must be closed

with EF for control channel errors to be reported.

Program STO to be longer than the time the ECU takes

to respond to opening of channel. Program ETO to be

longer than the time the ECU pauses between transac-

tions. As long as the ECU performs transactions, ETO is

reset and the channel stays open.

The ECU must wait 14 or more bit times before address-

ing another device during the same control channel ses-

sion. Failure to wait 14 bit times may result in the packet

boundary not being reset. Internal handshaking opera-

tions are automatically performed after the channel is

closed and before the video phase begins.

MAX9257/MAX9258

______________________________________________________________________________________ 33

Fully Programmable Serializer/Deserializer

with UART/I

C Control Channel

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P52

MAX9258GCM/V+

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