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MAX9258GCM/V+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
MAX9257/MAX9258
______________________________________________________________________________________ 37
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
PARAMETER SYMBOL MIN TYP MAX UNIT
SCL Clock Frequency f
SCL
11 t
UCLK*
Start Condition Hold Time t
HD:STA
11 t
UCLK
Low Period of SCL Clock t
LOW
0.5 0.5 t
UCLK
High Period of SCL Clock t
HIGH
0.5 0.5 t
UCLK
Repeated START Condition
Setup Time
t
SU:STA
0.25 0.25 t
UCLK
Data Hold Time t
HD:DAT
0.25 0.25 t
UCLK
Data Setup Time t
SU:DAT
0.25 0.25 t
UCLK
Setup Time for STOP Condition t
SU:STO
0.25 0.25 t
UCLK
Bus Free Time t
BUF
0.5 0.5 t
UCLK
Table 31. Timing Information for I
2
C Data Rates Greater than 400kbps
*
t
UCLK
is equal to one UART period.
I
2
C
The MAX9257 features a UART-to-I
2
C converter that
converts UART packets to I
2
C. The UART-to-I
2
C con-
verter works as a repeater between the ECU and exter-
nal I
2
C slave devices. The MAX9257 acts as the master
and converts UART read/write packets from the ECU to
I
2
C read/write for external I
2
C slave devices. For writes,
the UART-to-I
2
C converts the UART packets received
directly into I
2
C. For reads, the UART-to-I
2
C converter
follows the UART packet protocol. The I
2
C SCL clock
period is approximately the same as the UART bit clock
period (t
UCLK
). The I
2
C speed varies with UART speed.
I
2
C reads from the peripheral device do not disable the
ETO timer. Choose ETO large enough so that I
2
C read
commands are not lost due to ETO timing out.
I
2
C Timing
The MAX9257 acts like a master in I
2
C communication
with the peripheral device. The MAX9257 takes less
than 22 UART bit times to convert UART packets into
I
2
C. The SCL and SDA timings are based on the UART
bit clock. The I
2
C data rate is determined by UART and
can range from 95kbps to 4.25Mbps. The I
2
C timing
requirements scale linearly from fast mode to higher
speeds. Table 31 shows the I
2
C timing information for
data rates greater than 400kbps. The I
2
C parameters
scale with t
UCLK
. See Figure 30 for timing parameters.
Applications Information
PRBS Test
The MAX9257/MAX9258 have built-in circuits for testing
bit errors on the serial link. The MAX9257 has a PRBS
generator and the MAX9258 has a PRBS checker. The
length of the PRBS pattern is programmable from 2
21
to
2
35
word length or continuous by programming
REG9[7:4] in the MAX9257. In case of errors, errors are
counted in the MAX9258 PRBSERR register (REG12),
and the ERROR output on the MAX9258 goes low. To
start the test, the ECU writes a 1 to PRBSEN bit of both
the MAX9257 and the MAX9258. The PRBS test can be
MAX9257/MAX9258
38 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
performed with or without spread spectrum. If the PRBS
test is programmed to run continuously, the MAX9257
must be powered down to stop the test. When pro-
grammed for a finite number of repetitions, the control
channel is enabled after the PRBS test finishes and
serialization enable (SEREN) is reset to 0. To start nor-
mal operation, the ECU must disable PRBSEN and
enable SEREN.
Video Data Parity
Parity protection of video data is programmable for par-
allel-word widths of 16 bits or less. When programmed,
two parity bits are appended to each parallel word
latched into the MAX9257. In the MAX9258, a 16-bit
parity error counter logs parity errors. The ERROR out-
put on the MAX9258 goes low if parity errors exceed a
programmable threshold.
AC-Coupling Benefits
AC-coupling increases the input voltage of the LVDS
receiver to the voltage rating of the capacitor. Two
capacitors are sufficient for isolation, but four capaci-
tors—two at the serializer output and two at the deseri-
alizer input—provide protection if either end of the
cable is shorted to a high voltage. AC-coupling blocks
low-frequency ground shifts and common-mode noise.
Selection of AC-Coupling Capacitors
See Figure 31 for calculating the capacitor values for
AC-coupling depending on the parallel clock frequency.
The plot shows minimum capacitor values for two- and
four-capacitor-per-link systems. To block the highest
common-mode frequency shift, choose the minimum
capacitor value shown in Figure 31. In general, 0.1µF
capacitors are sufficient.
Optimally Choosing AC-Coupling Capacitors
Voltage droop and the digital sum variaton (DSV) of trans-
mitted symbols cause signal transitions to start from dif-
ferent voltage levels. Because the transition time is finite,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the LVDS receiver termination resistor (R
TR
),
AC-COUPLING CAPACITOR VALUE
vs. SERIAL-DATA RATE
SERIAL-DATA RATE (Mbps)
CAPACITOR VALUE (nF)
780720660600540480420
20
40
60
0
360 840
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
Figure 31. AC-Coupling Capacitor Values vs. Clock Frequency
from 18MHz to 42MHz
P
t
BUF
t
R
t
HD;STA
P
S
S
t
HD;STA
t
LOW
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
t
SU;STA
t
SU;STO
SCL
SDA
Figure 30. I
2
C Timing Parameters
MAX9257/MAX9258
______________________________________________________________________________________ 39
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
the LVDS driver termination resistor (R
TD
), and the series
AC-coupling capacitors (C). The RC time constant for
four equal-value series capacitors is (C x (R
TD
+ R
TR
))/4.
R
TD
and R
TR
are required to match the transmission line
impedance (usually 100Ω). This leaves the capacitor
selection to change the system time constant. In the fol-
lowing example, the capacitor value for a droop of 2% is
calculated:
where:
C = AC-coupling capacitor (F)
t
B
= bit time(s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
R
TD
= driver termination resistor (Ω)
R
TR
= receiver termination resistor (Ω)
The bit time (t
B
) is the serial-clock period or the period
of the pixel clock divided by the total number of bits.
The maximum DSV for the MAX9257 encoding equals
to the total number of bits transmitted in one pixel clock
cycle. This means that t
B
x DSV ≤ t
T
.
The capacitor for 2% maximum droop at 16MHz paral-
lel rate clock is:
Total number of bits is = 10 (data) + 2 (HSYNC and
VSYNC) + 2 (encoding) + 2 (parity) = 16
C ≥ 0.062µF
Jitter due to droop is proportional to the droop and tran-
sition time:
t
J
= t
TT
x D
where:
t
J
= jitter(s)
t
TT
= transition time(s) (0 to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
t
J
= 1ns x 0.02
t
J
= 20ps
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter. Use
high-frequency, surface-mount ceramic capacitors.
Power-Supply Circuits and Bypassing
All single-ended inputs and outputs on the MAX9257
are powered from V
CCIO
. All single-ended outputs on
the MAX9258 are powered from V
CCOUT
. V
CCIO
and
V
CCOUT
can be connected to a +1.71V to +3.6V sup-
ply. The input levels or output levels scale with these
supply rails.
Board Layout
Separate the LVCMOS/LVTTL signals and LVDS signals
to prevent crosstalk. A four-layer PCB with separate lay-
ers for power, ground, LVDS, and digital signals is rec-
ommended. Layout PCB traces for 100Ω differential
characteristic impedance. The trace dimensions
depend on the type of trace used (microstrip or
stripline). Note that two 50Ω PCB traces do not have
100Ω differential impedance when brought close
together—the impedance goes down when the traces
are brought closer.
Route the PCB traces for an LVDS channel (there are
two conductors per LVDS channel) in parallel to main-
tain the differential characteristic impedance. Place the
100Ω (typ) termination resistor at both ends of the
LVDS driver and receiver. Avoid vias. If vias must be
used, use only one pair per LVDS channel and place
the via for each line at the same point along the length
of the PCB traces. This way, any reflections occur at
the same time. Do not make vias into test points for
ATE. Make the PCB traces that make up a differential
pair the same length to avoid skew within the differen-
tial pair.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables offer superior signal quality compared to ribbon
cable and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise
as common mode that is rejected by the LVDS receiver.
C
ns
=
××
×+
-
-
4 3 91 16
1 02 100 100
.
ln( . ) ( )ΩΩ
C
tDSV
DR R
B
TR TD
=
××
×+
-
-
4
1ln( ) ( )
C
tDSV
DR R
B
TR TD
=−
××
×+
4
1ln( ) ( )-
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

MAX9258GCM/V+

Mfr. #:
Buy MAX9258GCM/V+
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes Prog Serializer / Deserializer
Lifecycle:
New from this manufacturer.
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