SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 10 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.1 Internal registers
The SC16C550B provides 12 internal registers for monitoring and control. These registers
are shown in Table 3
. These registers function as data holding registers (THR/RHR),
interrupt status and control registers (IER/ISR), a FIFO Control Register (FCR), line status
and control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
scratchpad register (SPR). Register functions are more fully described in the following
paragraphs.
[1] These registers are accessible only when LCR[7] is a logic 0.
[2] These registers are accessible only when LCR[7] is a logic 1.
6.2 FIFO operation
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
bit 0 (FCR[0]). With 16C550 devices, the user can set the receive trigger level, but not the
transmit trigger level. The receiver FIFO section includes a time-out function to ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached.
Table 3. Internal registers decoding
A2 A1 A0 Read mode Write mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR/LSR, SPR)
[1]
000Receive Holding Register Transmit Holding Register
001Interrupt Enable Register Interrupt Enable Register
010Interrupt Status Register FIFO Control Register
011Line Control Register Line Control Register
100Modem Control Register Modem Control Register
101Line Status Register n/a
110Modem Status Register n/a
111Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)
[2]
000LSB of Divisor Latch LSB of Divisor Latch
001MSB of Divisor Latch MSB of Divisor Latch
Table 4. Flow control mechanism
Selected trigger level
(characters)
INT pin activation Negate RTS Assert RTS
1110
4440
8880
14 14 14 0
SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 11 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.3 Autoflow control
Autoflow control is comprised of auto-CTS and auto-RTS (see Figure 6). With auto-CTS,
the CTS
input must be active before the transmitter FIFO can emit data. With auto-RTS,
RTS
becomes active when the receiver needs more data and notifies the sending serial
device. When RTS
is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using UART 1
and UART 2 from a SC16C550B with the autoflow control enabled. If not, overrun errors
occur when the transmit data rate exceeds the receiver FIFO read latency.
6.3.1 Auto-RTS
Auto-RTS data flow control originates in the receiver timing and control block (refer to
Figure 1 “
Block diagram of SC16C550B) and is linked to the programmed receiver FIFO
trigger level (see Figure 6
). When the receiver FIFO level reaches a trigger level of 1, 4,
or 8 (see Figure 8
), RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending
UART may send an additional byte after the trigger level is reached (assuming the
sending UART has another byte to send) because it may not recognize the de-assertion
of RTS
until after it has begun sending the additional byte. RTS is automatically
reasserted once the RX FIFO is emptied by reading the receiver buffer register. When the
trigger level is 14 (see Figure 9
), RTS is de-asserted after the first data bit of the 16th
character is present on the RX line. RTS
is reasserted when the RX FIFO has at least one
available byte space.
6.3.2 Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte (see Figure 6).
When CTS
is active, it sends the next byte. To stop the transmitter from sending the
following byte, CTS
must be released before the middle of the last stop bit that is currently
being sent (see Figure 7
). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS
level changes do not trigger host interrupts because
the device automatically controls its own transmitter. Without auto-CTS
, the transmitter
sends any data present in the transmit FIFO and a receiver overrun error may result.
Fig 6. Autoflow control (auto-RTS and auto-CTS) example
RX
FIFO
FLOW
CONTROL
TX
FIFO
PARALLEL
TO SERIAL
TX
FIFO
RX
FIFO
UART 1 UART 2
D7 to D0
RX TX
RTS CTS
TX RX
CTS RTS
D7 to D0
002aaa228
SERIAL TO
PARALLEL
SERIAL TO
PARALLEL
FLOW
CONTROL
FLOW
CONTROL
FLOW
CONTROL
PARALLEL
TO SERIAL
SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 12 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.3.3 Enabling autoflow control and auto-CTS
Autoflow control is enabled by setting MCR[5] and MCR[1].
6.3.4 Auto-CTS and auto-RTS functional timing
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in
Figure 8
and Figure 9.
Table 5. Enabling autoflow control and auto-CTS
MCR[5] MCR[1] Selection
1 1 auto RTS
and CTS
1 0 auto CTS
0 X disable
(1) When CTS is LOW, the transmitter keeps sending serial data out.
(2) If CTS
goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but
it does not send the next byte.
(3) When CTS
goes from HIGH to LOW, the transmitter begins sending data again.
Fig 7. CTS functional timing waveforms
(1) N = RX FIFO trigger level (1, 4, or 8 bytes).
(2) The two blocks in dashed lines cover the case where an additional byte is sent as described in Section 6.3.1
.
Fig 8. RTS functional timing waveforms, RX FIFO trigger level = 1, 4, or 8 bytes
Start byte N Start byte N + 1 Start byteStop Stop StopRX
RTS
IOR
N N + 1
12
002aaa050

SC16C550BIB48,128

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 1CH UART 16B FIFO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union