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SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 31 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Maximum frequency =
[3] Applicable only when AS
is tied LOW.
[4] RESET pulse must happen when these signals are inactive: CS0 or CS1 or CS2
or CS, and IOW, IOR.
t
18d
delay to set interrupt from Modem input 25 pF load - 100 - 24 - 23 ns
t
19d
delay to reset interrupt from IOR 25 pF load - 100 - 24 - 23 ns
t
20d
delay from stop to set interrupt - 1T
RCLK
-1T
RCLK
-1T
RCLK
s
t
21d
delay from IOR to reset interrupt 25 pF load - 100 - 29 - 28 ns
t
22d
delay from start to set interrupt - 100 - 45 - 40 ns
t
23d
delay from IOW to transmit start 8T
RCLK
24T
RCLK
8T
RCLK
24T
RCLK
8T
RCLK
24T
RCLK
s
t
24d
delay from IOW to reset interrupt - 100 - 45 - 40 ns
t
25d
delay from stop to set RXRDY -1T
RCLK
-1T
RCLK
-1T
RCLK
s
t
26d
delay from IOR to reset RXRDY - 100 - 45 - 40 ns
t
27d
delay from IOW to set TXRDY - 100 - 45 - 40 ns
t
28d
delay from start to reset TXRDY -8T
RCLK
-8T
RCLK
-8T
RCLK
s
t
RESET
RESET pulse width
[4]
100 - 40 - 40 - ns
N baud rate divisor 1 2
16
11 2
16
11 2
16
1
Table 26. Dynamic characteristics …continued
T
amb
=
40
C to +85
C; tolerance of V
DD
10 %, unless otherwise specified.
Symbol Parameter Conditions V
DD
= 2.5 V V
DD
= 3.3 V V
DD
= 5.0 V Unit
Min Max Min Max Min Max
