SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 6 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
5.2 Pin description
Table 2. Pin description
Symbol Pin Type Description
PLCC44 LQFP48 DIP40 HVQFN32
A0 31 28 28 19 I Register select. A2 to A0 are used during read and write
operations to select the UART register to read from or
write to. Refer to Table 3
for register addresses and refer
to AS
description.
A1 30 27 27 18
A2 29 26 26 17
AS
28 24 25 - I Address strobe. When AS is active (LOW), A0, A1, and
A2 and CS0, CS1, and CS2 drive the internal select logic
directly; when AS is HIGH, the register select and chip
select signals are held at the logic levels they were in
when the LOW-to-HIGH transition of AS
occurred.
BAUDOUT
17 12 15 - O Baud out. BAUDOUT is a 16 clock signal for the
transmitter section of the UART. The clock rate is
established by the reference oscillator frequency divided
by a divisor specified in the baud generator divisor latches.
BAUDOUT
may also be used for the receiver section by
tying this output to RCLK. In HVQFN32 package
BAUDOUT
and RCLK are bonded internally.
CS0
[2]
14 9 12 - I Chip select. When CS0 and CS1 are HIGH and CS2 is
LOW, these three inputs select the UART. When any of
these inputs are inactive, the UART remains inactive (refer
to AS
description).
CS1
[2]
15 10 13 -
CS2
[2]
16 11 14 -
CS
[2]
---8
CTS
[2]
40 38 36 24 I Clear to send. CTS is a modem status signal. Its condition
can be checked by reading bit 4 (CTS
) of the Modem
Status Register. Bit 0 (CTS) of the Modem Status Register
indicates that CTS has changed states since the last read
from the Modem Status Register. If the modem status
interrupt is enabled when CTS
changes levels and the
auto-CTS mode is not enabled, an interrupt is generated.
This pin has no effect on the UART’s transmit or receive
operation.
D7 to D0 9, 8, 7,
6, 5, 4,
3, 2
4, 3, 2,
47, 46,
45, 44,
43
8, 7,
6, 5,
4, 3,
2, 1
5, 4, 3, 1,
32, 31, 30,
29
I/O Data bus. Eight data lines with 3-state outputs provide a
bidirectional path for data, control and status information
between the UART and the CPU.
DCD
[2]
42 40 38 26 I Data carrier detect. DCD is a modem status signal. Its
condition can be checked by reading bit 7 (DCD
) of the
Modem Status Register. Bit 3 (DCD
) of the Modem Status
Register indicates that DCD
has changed states since the
last read from the Modem Status Register. If the modem
status interrupt is enabled when DCD
changes levels, an
interrupt is generated.
DDIS
26 22 23 - O Driver disable. DDIS is active (LOW) when the CPU is
reading data. When inactive (HIGH), DDIS
can disable an
external transceiver.
