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SC16C550BIB48,128

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49
SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 13 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.4 Hardware/software and time-out interrupts
Following a reset, the transmitter interrupt is enabled, the SC16C550B will issue an
interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be
serviced prior to continuing operations. The ISR register provides the current singular
highest priority interrupt only. Only after servicing the higher pending interrupt will the
lower priority be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C550B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
center of each stop bit received or each time the Receive Holding Register (RHR) is read.
The actual time-out value is 4 character time, including data information length, start bit,
parity bit, and the size of stop bit, that is, 1, 1.5, or 2 bit times.
(1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the
sixteenth byte.
(2) RTS
is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is more
than one byte of space available.
(3) When the receive FIFO is full, the first receive buffer register read re-asserts RTS
.
Fig 9. RTS functional timing waveforms, RX FIFO trigger level = 14 bytes
byte 14 byte 15RX
RTS
IOR
Start byte 18 StopStart byte 16 Stop
002aaa051
RTS released after the
first data bit of byte 16
SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 14 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.5 Programmable baud rate generator
The SC16C550B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.
The SC16C550B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable baud rate generator is capable of
accepting an input clock up to 48 MHz, as required for supporting a 3 Mbit/s data rate.
The SC16C550B can be configured for internal or external clock operation. For internal
clock oscillator operation, an industry standard microprocessor crystal is connected
externally between the XTAL1 and XTAL2 pins (see Figure 10
). Alternatively, an external
clock can be connected to the XTAL1 pin to clock the internal baud rate generator for
standard or custom rates (see Table 6
).
The generator divides the input 16 clock by any divisor from 1 to (2
16
1). The
SC16C550B divides the basic crystal or external clock by 16. The frequency of the
BAUDOUT
output pin is exactly 16 (16 times) the selected baud rate
(BAUDOUT
=16 baud rate). Customized baud rates can be achieved by selecting the
proper divisor values for the MSB and LSB sections of the baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The examples in Table 6
shows
selectable baud rates when using a 1.8432 MHz crystal.
For custom baud rates, the divisor value can be calculated using the following equation:
(1)
Fig 10. Crystal oscillator connection
002aaa870
C2
47 pF
XTAL1 XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
XTAL1 XTAL2
1.5 kΩ
X1
1.8432 MHz
C1
22 pF
divisor in decimal
XTAL1 clock frequency
serial data rate 16
---------------------------------------------------------------
=
SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 15 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.6 DMA operation
The SC16C550B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY
and TXRDY output
pins. Table 7
and Table 8 show this.
Remark: DMA operation is not supported in the HVQFN32 package.
Table 6. Baud rates using 1.8432 MHz or 3.072 MHz crystal
Using 1.8432 MHz crystal Using 3.072 MHz crystal
Desired baud
rate
Divisor for
16 clock
Baud rate
error
Desired baud
rate
Divisor for
16 clock
Baud rate
error
50 2304 50 3840
75 1536 75 2560
110 1047 0.026 110 1745 0.026
134.5 857 0.058 134.5 1428 0.034
150 768 150 1280
300 384 300 640
600 192 600 320
1200 96 1200 160
1800 64 1800 107 0.312
2000 58 0.69 2000 96
2400 48 2400 80
3600 32 3600 53 0.628
4800 24 4800 40
7200 16 7200 27 1.23
9600 12 9600 20
19200 6 19200 10
38400 3 38400 5
56000 2 2.86
Table 7. Effect of DMA mode on state of RXRDY pin
Non-DMA mode DMA mode
1 = FIFO empty 0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
Table 8. Effect of DMA mode on state of TXRDY
pin
Non-DMA mode DMA mode
1 = at least 1 byte in FIFO 1 = FIFO is full
0 = FIFO empty 0 = FIFO is empty
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49

SC16C550BIB48,128

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Buy SC16C550BIB48,128
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 1CH UART 16B FIFO
Lifecycle:
New from this manufacturer.
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