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SC16C550BIB48,128

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49
SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 28 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.9 Scratchpad Register (SPR)
The SC16C550B provides a temporary data register to store 8 bits of user information.
7.10 SC16C550B external reset conditions
8. Limiting values
Table 22. Reset state for registers
Register Reset state
IER IER[7:0] = 0
ISR ISR[7:1] = 0; ISR[0] = 1
LCR LCR[7:0] = 0
MCR MCR[7:0] = 0
LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR MSR[7:4] = input signals; MSR[3:0] = 0
FCR FCR[7:0] = 0
Table 23. Reset state for outputs
Output Reset state
TX HIGH
RTS
HIGH
DTR
HIGH
RXRDY
HIGH
TXRDY
LOW
Table 24. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage - 7 V
V
n
voltage on any other pin at D7 to D0 pins V
SS
0.3 V
DD
+0.3 V
at any input only pin V
SS
0.3 5.3 V
T
amb
ambient temperature operating in free air 40 +85 C
T
stg
storage temperature 65 +150 C
P
tot
/pack total power dissipation
per package
-500mW
SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 29 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
9. Static characteristics
[1] Except for XTAL2, V
OL
=1V typically.
Table 25. Static characteristics
T
amb
=
40
C to +85
C; tolerance of V
DD
=
10 %, unless otherwise specified.
Symbol Parameter Conditions V
DD
=2.5V V
DD
=3.3V V
DD
=5.0V Unit
Min Max Min Max Min Max
V
IL(clk)
clock LOW-level input voltage 0.3 +0.45 0.3 +0.6 0.5 +0.6 V
V
IH(clk)
clock HIGH-level input voltage 1.8 V
DD
2.4 V
DD
3.0 V
DD
V
V
IL
LOW-level input voltage 0.3 +0.65 0.3 +0.8 0.5 +0.8 V
V
IH
HIGH-level input voltage 1.6 - 2.0 - 2.2 V
DD
V
V
OL
LOW-level output voltage on all outputs
[1]
I
OL
=5mA
(data bus)
-----0.4V
I
OL
=4mA
(other outputs)
---0.4--V
I
OL
=2mA
(data bus)
-0.4----V
I
OL
=1.6mA
(other outputs)
-0.4----V
V
OH
HIGH-level output voltage I
OH
= 5mA
(data bus)
----2.4-V
I
OH
= 1mA
(other outputs)
--2.0---V
I
OH
= 800 A
(data bus)
1.85 - - - - - V
I
OH
= 400 A
(other outputs)
1.85 - - - - - V
I
LIL
LOW-level input leakage
current
- 10 - 10 - 10 A
I
L(clk)
clock leakage current - 30 - 30 - 30 A
I
DD(AV)
average supply current f = 5 MHz - 3.5 - 4.5 - 4.5 mA
C
i
input capacitance - 5 - 5 - 5 pF
R
pu(int)
internal pull-up resistance 500 - 500 - 500 - k
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SC16C550B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 16 December 2014 30 of 49
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
10. Dynamic characteristics
Table 26. Dynamic characteristics
T
amb
=
40
C to +85
C; tolerance of V
DD
10 %, unless otherwise specified.
Symbol Parameter Conditions V
DD
= 2.5 V V
DD
= 3.3 V V
DD
= 5.0 V Unit
Min Max Min Max Min Max
t
w1
clock pulse duration 15 - 13 - 10 - ns
t
w2
clock pulse duration 15 - 13 - 10 - ns
f
XTAL
clock frequency
[1][2]
-16-32-48MHz
t
4w
address strobe width 45 - 35 - 25 - ns
t
5s
address setup time 5 - 5 - 1 - ns
t
5h
address hold time 5 - 5 - 5 - ns
t
6s
chip select setup time to AS 10-5-0-ns
t
6h
address hold time 0 - 0 - 0 - ns
t
6s'
address setup time
[3]
10 - 10 - 5 - ns
t
6h
chip select hold time 0 - 0 - 0 - ns
t
7d
IOR delay from chip select 10 - 10 - 10 - ns
t
7w
IOR strobe width 25 pF load 77 - 26 - 23 - ns
t
7h
chip select hold time from IOR 0- 0- 0- ns
t
7h'
address hold time
[3]
5- 5- 5- ns
t
8d
IOR delay from address 10 - 10 - 10 - ns
t
9d
read cycle delay 25 pF load 20 - 20 - 20 - ns
t
11d
IOR to DDIS delay 25 pF load - 100 - 35 - 30 ns
t
12d
delay from IOR to data 25 pF load - 77 - 26 - 23 ns
t
12h
data disable time 25 pF load - 15 - 15 - 15 ns
t
13d
IOW delay from chip select 10 - 10 - 10 - ns
t
13w
IOW strobe width 20 - 20 - 15 - ns
t
13h
chip select hold time from IOW 0- 0- 0- ns
t
14d
IOW delay from address 10 - 10 - 10 - ns
t
15d
write cycle delay 25 - 25 - 20 - ns
t
16s
data setup time 20 - 20 - 15 - ns
t
16h
data hold time 15 - 5 - 5 - ns
t
17d
delay from IOW to output 25 pF load - 100 - 33 - 29 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49

SC16C550BIB48,128

Mfr. #:
Buy SC16C550BIB48,128
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 1CH UART 16B FIFO
Lifecycle:
New from this manufacturer.
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