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NB3N1200KMNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
NB3N1200K, NB3W1200L
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10
Table 6. LOW BAND PHASE JITTER − PLL MODE
Group Parameter Min Typ Max Units
DIF
(Notes 14, 16, 17)
Output PCIe Gen1 13 86 ps
(p−p)
DIF
(Notes 14, 15, 17, 19)
Output PCIe Gen2 Low Band, 10 kHz < f < 1.5 MHz 0.1 3.0 ps
RMS
DIF
(Notes 14, 15, 17, 19)
Output PCIe Gen2 High Band, 1.5 MHz < f < 50 MHz 0.8 3.1 ps
RMS
HIGH BAND, 1.5 MHz < F < Nyquist
DIF
(Notes 14, 15, 17, 19)
Output phase jitter impact – PCIe* Gen3
(including PLL BW 2 – 4 MHz, CDR = 10 MHz)
0.18 1.0 ps
RMS
DIF
(Notes 14, 15, 17, 19)
Output phase jitter impact – PCIe* Gen4
(including PLL BW 2 – 4 MHz, CDR = 10 MHz)
0.18 0.5 ps
RMS
DIF
(Notes 14, 18)
Output Intel UPI intermediate frequency accumulated jitter
(9.6 Gb/s, 10.4 Gb/s or 11.2 Gb/s, 100 MHz, 12 UI)
0.5 1.0 ps
RMS
DIF
(Notes 14, 18, 20)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(4.8 Gb/s or 6.4 Gb/s, 100 MHz or 133 MHz, 12 UI)
0.14 0.5 ps
RMS
DIF
(Notes 14, 18)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(8 Gb/s, 100 MHz, 12 UI)
0.07 0.3 ps
RMS
DIF
(Notes 14, 18)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(9.6 Gb/s, 100 MHz, 12 UI)
0.06 0.2 ps
RMS
Table 7. ADDITIVE PHASE JITTER − BYPASS MODE
Group Parameter Min Typ Max Units
DIF
(Notes 14, 16, 17)
Output PCIe Gen1 0.04 10 ps
(p−p)
DIF
(Notes 14, 15, 17, 19)
Output PCIe Gen2 Low Band, 10 kHz < f < 1.5 MHz 0.001 0.3 ps
RMS
DIF
(Notes 14, 15, 17, 19)
Output PCIe Gen2 High Band, 1.5 MHz < f < 50 MHz 0.002 0.7 ps
RMS
DIF
(Notes 14, 15, 17, 19)
Output phase jitter impact – PCIe* Gen3 0.001 0.3 ps
RMS
DIF
(Notes 14, 15, 17, 19)
Output phase jitter impact – PCIe* Gen4 0.001 0.3 ps
RMS
DIF
(Notes 14, 18, 20)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(4.8 Gb/s or 6.4 Gb/s, 100 MHz or 133 MHz, 12 UI)
0.001 0.3 ps
RMS
DIF
(Notes 14, 18)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(8 Gb/s, 100 MHz, 12 UI)
0.001 0.1 ps
RMS
DIF
(Notes 14, 18)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(9.6 Gb/s, 100 MHz, 12 UI)
0.001 0.1 ps
RMS
14.Post processed evaluation through Intel supplied Matlab scripts. Tested with NB3N1200K/NB3W1200L driven by a CK420BQ or equivalent.
15.PCIe Gen4 filter characteristics are subject to final ratification by PCISIG. Please check the PCI SIG for the latest specification.
16.These jitter numbers are defined for a BER of 1E−12. Measured numbers at a smaller sample size have to be extrapolated to this BER target.
17.⎛ = 0.54 is implying a jitter peaking of 3 dB.
18.Measuring on 100 MHz output using Intel supplied clock template jitter tool.
19.Measuring on 100 MHz PCIe SRC output using Intel supplied clock jitter tool.
20.Measuring on 100 MHz, 133 MHz output using Intel supplied clock jitter tool.
Table 8. PLL BANDWIDTH AND PEAKING
Group Parameter Min Typ Max Units
DIF (Note 21) PLL Jitter Peaking (HBW_BYPASS_LBW# = 0) − 0.7
2.0
dB
DIF (Note 21) PLL Jitter Peaking (HBW_BYPASS_LBW# = 1) − 0.4
2.5
dB
DIF (Note 22) PLL Bandwidth (HBW_BYPASS_LBW# = 1) 2.0 2.7 4.0 MHz
DIF (Note 22) PLL Bandwidth (HBW_BYPASS_LBW# = 0) 0.7 0.9
1.4
MHz
21.Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
22.Measured at 3 db down or half power point.
NB3N1200K, NB3W1200L
www.onsemi.com
11
Table 9. DIF 0.7 V AC TIMING CHARACTERISTICS (Non−Spread or −0.5% Spread Spectrum Mode)
(V
DD
= V
DDA
= V
DDR
= 3.3 V ±5%)
Symbol
Parameter
CLK = 100 MHz, 133.33 MHz
Unit
Min Max
Tstab (Note 44) Clock Stabilization Time 1.8 ms
Laccuracy (Notes 26, 30, 38, 45) Long Accuracy 100 ppm
Tabs (Notes 26, 27, 30) Absolute
Min/Max
Host CLK
Period
No Spread
9.94900 for 100 MHz 10.05100 for 100 MHz
ns
7.44925 for 133 MHz 7.55075 for 133 MHz
−0.5% Spread
9.49900 for 100 MHz 10.10126 for 100 MHz
7.44925 for 133 MHz 7.58845 for 133 MHz
Slew_rate (Notes 24, 26, 30) DIFF OUT Slew_rate (see Figure 4) 1.0 4.0 V/ns
DTrise / DTfall (Notes 26, 29, 40)
Rise and Fall Time Variation 125 ps
Rise/Fall Matching (Notes 26, 30, 41, 43) 20 %
VHigh (Notes 26, 29, 32)
Voltage High (typ 0.70 Volts)
660 850 mV
VLow (Notes 26, 29, 33)
Voltage Low (typ 0.0 Volts)
−150 150 mV
Vmax (Note 29) Maximum Voltage 1150 mV
Vcross absolute (Notes 23, 25, 26, 29, 36) Absolute Crossing Point Voltages 250 550 mV
Vcross relative (Notes 26, 28, 29, 36) Relative Crossing Point Voltages Calc Calc
Total D Vcross (Notes 26, 29, 37)
Total Variation of Vcross
Over All Edges
140 mV
Tccjitter (Notes 26, 30, 42) Cycle−to−Cycle Jitter 50 ps
Duty Cycle (Notes 26, 30) PLL and Bypass Modes 45 55 %
tOE# Latency OE# Latency − DIFF start after OE#
Assertion
− DIFF stop after OE# Deassertion
4 12 Clocks
Vovs (Notes 26, 29, 34) Maximum Voltage (Overshoot) Vhigh + 0.3 V
Vuds (Notes 26, 29, 35) Maximum Voltage (Undershoot) Vlow − 0.3 V
Vrb (Notes 26, 29) Ringback Voltage 0.2 N/A V
23.Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.
24.Measurment taken from differential waveform on a component test board. The slew rate is measured from −150 mV to +150 mV on the
differential waveform. Scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge
Only valid for Rising CLK_IN and Falling CLK_IN#. Signal must be monotonic through the Vol to Voh region for Trise and Tfall.
25.This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
26.Test configuration is Rs = 33.2 W, Rp = 49.9, 2 pF for 100 W transmission line; Rs = 27 W, Rp = 42.2, 2 pF for 85 W transmission line.
27.The average period over any 1 ms period of time must be greater than the minimum and less than the maximum specified period.
28.Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg − 0.700), Vcross(rel) Max = 0.550 − 0.5 (0.700
– Vhavg), (see Figure 7).
29.Measurement taken from Single Ended waveform.
30.Measurement taken from differential waveform. Bypass mode, input duty cycle = 50%.
31.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
32.VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
33.VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
34.Overshoot is defined as the absolute value of the maximum voltage.
35.Undershoot is defined as the absolute value of the minimum voltage.
36.The crossing point must meet the absolute and relative crossing point specifications simultaneously.
37.DVcross is defined as the total variation of all crossing voltages of Rising DIFF and Falling DIFF#. This is the maximum allowed variance
in Vcross for any particular system.
38.Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 100,000,000 Hz, 133,333,333 Hz.
39.Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz.
40.Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
41.Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of DIFF versus the falling edge rate
(average) of DIFF#. Measured in a ±75 mV window around the crosspoint of DIFF and DIFF#.
42.Measured with device in PLL mode, in BYPASS mode jitter is additive.
43.Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).
44.This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8 V – 2.0 V to the time that stable clocks
are output from the buffer chip (PLL locked).
45.All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ accuracy
requirements. The NB3N1200K and NB3W1200L itself do not contribute to ppm error.
NB3N1200K, NB3W1200L
www.onsemi.com
12
Table 10. CLOCK PERIOD SSC DISABLED
SSC OFF
Center
Freq.
MHz
Measurement Window
Units
1 Clock
1 ms
0.1 s 0.1 s 0.1 s
1 ms
1 Clock
− Jitter c−c
Abs Per Min
− SSC Short
Avg Min
− ppm Long
Avg Min
0 ppm
Period
+ ppm Long
Avg Max
+ SSC Short
Avg Max
+ Jitter c−c
Abs Per Max
100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns
133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns
Table 11. CLOCK PERIOD SSC ENABLED
SSC ON
Center
Freq.
MHz
Measurement Window
Units
1 Clock
1 ms
0.1 s 0.1 s 0.1 s
1 ms
1 Clock
− Jitter c−c
Abs Per Min
− SSC Short
Avg Min
− ppm Long
Avg Min
0 ppm
Period
+ ppm Long
Avg Max
+ SSC Short
Avg Max
+ Jitter c−c
Abs Per Max
99.75
9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126 ns
133.00 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845 ns
Table 12. INPUT EDGE RATE (Note 46)
Frequency Select (FS)
Min Max Unit
100 MHz 0.35 N/A V/ns
133 MHz 0.35 N/A V/ns
46.Input edge rate is based on single ended measurement. This is the minimum input edge rate at which the NB3N1200K / NB3W1200L devices
are guaranteed to meet all performance specifications.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

NB3N1200KMNTXG

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Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V 100/133MHz Diff 1:12 HCSL
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