OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NB3N1200KMNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
NB3N1200K, NB3W1200L
www.onsemi.com
7
Table 2. NB3W1200L PIN DESCRIPTIONS
Pin Number DescriptionTypePin Name
34 DIF_4 O, DIF 0.7 V Differential True clock output
35 DIF_4# O, DIF 0.7 V Differential Complementary clock output
36 OE_4# I, SE
3.3 V LVTTL active low input for enabling DIF output pair 4.
0 enables outputs, 1 disables outputs. Internal pull down.
37 OE_5# I, SE
3.3 V LVTTL active low input for enabling DIF output pair 5.
0 enables outputs, 1 disables outputs. Internal pull down.
38 DIF_5 O, DIF 0.7 V Differential True clock output
39 DIF_5# O, DIF 0.7 V Differential Complementary clock output
40 VDD 3.3 V 3.3 V power supply for core.
41 GND GND Ground for outputs.
42 DIF_6 O, DIF 0.7 V Differential True clock output
43 DIF_6# O, DIF 0.7 V Differential Complementary clock output
44 OE_6# I, SE
3.3 V LVTTL active low input for enabling DIF output pair 6.
0 enables outputs, 1 disables outputs. Internal pull down.
45 OE_7# I, SE
3.3 V LVTTL active low input for enabling DIF output pair 7.
0 enables outputs, 1 disables outputs. Internal pull down.
46 DIF_7 O, DIF 0.7 V Differential True clock output
47 DIF_7# O, DIF 0.7 V Differential Complementary clock output
48 GND GND Ground for outputs.
49 VDD_IO VDD Power supply for differential outputs.
50 DIF_8 O, DIF 0.7 V Differential True clock output
51 DIF_8# O, DIF 0.7 V Differential Complementary clock output
52 OE_8# I, SE
3.3 V LVTTL active low input for enabling DIF output pair 8.
0 enables outputs, 1 disables outputs. Internal pull down.
53 OE_9# I, SE
3.3 V LVTTL active low input for enabling DIF output pair 9.
0 enables outputs, 1 disables outputs. Internal pull down.
54 DIF_9 O, DIF 0.7 V Differential True clock output
55 DIF_9# O, DIF 0.7 V Differential Complementary clock output
56 VDD_IO VDD Power supply for differential outputs.
57 VDD 3.3 V 3.3 V power supply for core.
58 GND GND Ground for outputs.
59 DIF_10 O, DIF 0.7 V Differential True clock output
60 DIF_10# O, DIF 0.7 V Differential Complementary clock output
61 OE_10# I, SE
3.3 V LVTTL active low input for enabling DIF output pair 10.
0 enables outputs, 1 disables outputs. Internal pull down.
62 OE_11# I, SE
3.3 V LVTTL active low input for enabling DIF output pair 11.
0 enables outputs, 1 disables outputs. Internal pull down.
63 DIF_11 O, DIF 0.7 V Differential True clock output
64 DIF_11# O, DIF 0.7 V Differential Complementary clock output
EP Exposed Pad Thermal The Exposed Pad (EP) on the QFN−64 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is electrically connected to the die,
and must be electrically and thermally connected to GND on the PC board.
NB3N1200K, NB3W1200L
www.onsemi.com
8
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition Min Max Units
V
DD
/V
DDA
/V
DDR
Core Supply Voltage 4.6 V
V
DD_IO
I/O Supply Voltage 4.6 V
V
IH
(Note 1) Input High Voltage 4.6 V
V
IHSMB
SMB Input High Voltage SDA, SCL Pins 5.5 V
V
IL
3.3 V Input Low Voltage
−0.5 V
ts Storage Temperature −65 150 °C
ESD prot.
Input ESD protection Human Body Model 2000 V
q
JA
Thermal Resistance
(Junction−to−Ambient)
0 lfpm
500 lfpm
22
15
°C/W
I
OUTmax
Maximum Output Current
NB3N1200K
NB3W1200L
Powerdown Mode
(PWRGD/PWRDN# = 0)
All Pairs Tri−stated
All Pairs Tri−state Low/Low
24
12
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum VIH is not to exceed maximum VDD.
Table 4. DC OPERATING CHARACTERISTICS (V
DD
= V
DDA
= V
DDR
= 3.3 V ±5%, T
A
= 0°C − 70°C)
Symbol
Parameter Condition Min Max Units
V
DD
/V
DDA
/V
DDR
3.3 V Core Supply Voltage
3.3 V ±5% 3.135 3.465 V
V
DD_IO
(Note 2) I/O Supply Voltage 1.05 V to 3.3 V ±5% 0.975 3.465 V
I
DD
Power Supply Current
NB3N1200K
NB3W1200L
At 133 MHz, C
L
= 2 pF
330
180
mA
I
DDPD
Power Down Current
NB3N1200K
NB3W1200L
6
6
mA
V
IH
(Note 3) Input High Voltage, Single−Ended Inputs 2.0 5.5 V
V
IL
(Note 3) Input Low Voltage, Single−Ended Inputs GND−0.3 0.8 V
V
IHCLK_IN
CLK_IN/CLK_IN# High 600 1150 mV
V
ILCLK_IN
CLK_IN/CLK_IN# Low −300 300 mV
I
IL
(Note 4) Input Leakage Current 0 < V
IN
< V
DD
−5 +5
mA
VIH_FS (Note 5) Input High Voltage
0.7
V
DD
+0.3 V
VIL_FS (Note 5) Input Low Voltage GND−0.3 0.35 V
V
IL_Tri
(Note 6) Tri−Level Input Low Voltage 0 0.8 V
V
IM_Tri
(Note 6) Tri−Level Input Med Voltage
1.2
1.8 V
V
IH_Tri
(Note 6) Tri−Level Input High Voltage
2.2
V
DD
V
V
OH
(Note 7) Output High Voltage SCL, SDA I
OH
= −1 mA
2.4
V
V
OL
(Note 7) Output Low Voltage SCL, SDA I
OL
= 1 mA 0.4 V
C
in
(Note 8) Input Capacitance 2.5 4.5 pF
C
out
(Note 8) Output Capacitance 2.5 4.5 pF
L
pin
Pin Inductance 7 nH
ta Ambient Temperature No Airflow 0 70 °C
2. V
DD_IO
applies to the low power NMOS push−pull NB3W1200L only.
3. SDA, SCL, OEn#, PWRGD/PWRDN#.
4. Input Leakage Current does not include inputs with pull−up or pull−down resistors.
5. 100M_133M# Frequency Select (FS).
6. SA_0, SA_1, HBW_BYPASS_LBW#.
7. Signal edge is required to be monotonic when transitioning through this region.
8. Ccomp capacitance based on pad metallization and silicon device capacitance. Not including package pin capacitance.
NB3N1200K, NB3W1200L
www.onsemi.com
9
NB3N1200K / NB3W1200L Output Relational Timing Parameters
Table 5. ELECTRICAL CHARACTERISTICS − Skew and Differential Jitter Parameters
(V
DD
= V
DDA
= V
DDR
= 3.3 V ±5%, T
A
= 0 − 70°C)
Group
Description Min Typ Max Units
CLK_IN, DIF[x:0]
(Notes 9, 10, 12, 13)
Input−to−Output Delay in PLL mode, nominal value −100 100 ps
CLK_IN, DIF[x:0]
(Notes 10, 11, 13)
Input−to−Output Delay in Bypass mode, nominal value 2.5 4.5 ns
CLK_IN, DIF[x:0]
(Notes 10, 11, 13)
Input−to−Output Delay variation in PLL mode
(over voltage and temperature), nominal value
|100| ps
CLK_IN, DIF[x:0]
(Notes 10, 11, 13)
Input−to−Output Delay variation in Bypass mode
(over voltage and temperature), nominal value
|250| ps
DIF[11:0]
(Notes 9, 10, 11, 13)
Output−to−Output Skew across all 12 outputs
(Common to Bypass and PLL mode)
0 50 ps
9. Measured into fixed 2 pF load capacitance. Input to output skew is measured at the first output edge following the corresponding input.
10.Measured from differential cross−point to differential cross−point.
11. All Bypass Mode Input−to−Output specs refer to the timing between an input edge and the specific output edge created by it.
12.This parameter is deterministic for a given device.
13.Measured with scope averaging on to find mean value.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

NB3N1200KMNTXG

Mfr. #:
Buy NB3N1200KMNTXG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V 100/133MHz Diff 1:12 HCSL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet