NB3N1200K, NB3W1200L
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19
Byte Read/Write
Reading or writing a register in a SMBus slave device in
byte mode always involves specifying the register number.
Read. The standard byte read is as shown in the following
figure. It is an extension of the byte write. The write start
condition is repeated then the slave device starts sending
data and the master acknowledges it until the last byte is sent.
The master terminates the transfer with a NAK, then a stop
condition. For byte operation, the 2*7
th
bit of the command
byte must be set. For block operations, the 2*7
th
bit must be
reset. If the bit is not set, the next byte must be the byte
transfer count.
Figure 13. Byte Read Protocol
T Slave Wr A Command A r Slave Rd A Data Byte 0
Byte Read Protocol
N P
17118 117 811 11
starT
Condition
Command
stoP
Condition
Acknowledge
Not ackRepeat starT
Register # to read
2*7 bit = 1
Write. The following figure illustrates a simple typical byte
write. For byte operation
the 2*7th bit of the command byte
must be set
. For block operations, the 2*7th bit must be reset.
If the bit is not set, the next byte must be the byte transfer
count. The count can be between 1 and 32. It is not allowed
to be zero or exceed 32.
Figure 14. Byte Write Protocol
T Slave Wr A Command A Data Byte 0
Byte Write Protocol
A P
17118 1 811
starT
Condition Command
stoP
Condition
Acknowledge
Register # to write
2*7 bit = 1
M to
S to
Master to
Slave to
Block Read/Write
Read. After the slave address is sent with the r/w condition
bit set, the command byte is sent with the MSB = 0. The slave
Ack’s the register index in the command byte. The master
sends a repeat start function. After the slave Ack’s this, the
slave sends the number of bytes it wants to transfer (>0 and
<33). The master Ack’s each byte except the last and sends
a stop function.
Figure 15. Block Read Protocol
T Slave Wr A Command Code A
Block Read Protocol
17118 1
starT
Condition Command
Acknowledge
Register # to write
2*7 bit = 0
Data Byte A A Data Byte 1 N P
81 8 1 8 11
stoP
Condition
Data Byte 0
Not acknowledge
r Slave Rd A
1711
repeat starT Condition
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20
Write. After the slave address is sent with the r/w condition
bit not set, the command byte is sent with the MSB = 0. The
lower seven bits indicate what register to start the transfer at.
If the command byte is 00h, the slave device will be
compatible with existing block mode slave devices. The
next byte of a write must be the count of bytes that the master
will transfer to the slave device. The byte count must be
greater than zero and less than 33. Following this byte are the
data bytes to be transferred to the slave device. The slave
device always acknowledges each byte received. The
transfer is terminated after the slave sends the Ack and the
master sends a stop function.
Figure 16. Block Write Protocol
T Slave Address Wr A Command A
Block Write Protocol
17118 1
starT
Condition
Command bit
Acknowledge
Register # to write
2*7 bit = 0
M to
S to
Master to
Slave to
Byte Count = 2 A A Data Byte 1 A P
81 8 1 8 11
stoP
Condition
Data Byte 0
NB3N1200K/NB3W1200L Control Register
Table 21. BYTE 0: FREQUENCY SELECT, OUTPUT ENABLE, PLL MODE CONTROL REGISTER
Bit Description If Bit = 0 If Bit = 1 Type Default
Output(s)
Affected
0 100M_133M# Frequency Select (FS) 133 MHz 100 MHz R Latched at
power up
DIF[11:0]
1 PLL Mode 0
See PLL Operating Mode
Readback Table
RW 1
2 PLL Mode 1 RW 1
3 PLL Software Enable HW Latch SMBUS Control RW 0
4 Reserved 0
5 Reserved 0
6 PLL Mode 0 See PLL Operating Mode
Readback Table
R Latched at
power up
7 PLL Mode 1 See PLL Operating Mode
Readback Table
R Latched at
power up
NOTE: Byte 0, bit_[3:1] are BW PLL SW enable for the NB3W1200L and NB3N1200K. Setting bit 3 to ‘1’ allows the
user to override the Latch value from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating Mode
Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. A warm reset of the
system will have to be accomplished if the user changes these bits.
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21
Table 22. BYTE 1: OUTPUT ENABLE CONTROL REGISTER
Bit Description
If Bit = 0
If Bit = 1 Type Default
Output(s)
Affected
0
Output Enable DIF 0 Hi−Z for NB3N1200K
Enabled RW 1 DIF_0,
DIF_0#
Low/Low for NB3W1200L
1 Output Enable DIF 1
Hi−Z for NB3N1200K
Enabled RW 1 DIF_1,
DIF_1#
Low/Low for NB3W1200L
2 Output Enable DIF 2
Hi−Z for NB3N1200K
Enabled RW 1 DIF_2,
DIF_2#
Low/Low for NB3W1200L
3 Output Enable DIF 3
Hi−Z for NB3N1200K
Enabled RW 1 DIF_3,
DIF_3#
Low/Low for NB3W1200L
4 Output Enable DIF 4
Hi−Z for NB3N1200K
Enabled RW 1 DIF_4,
DIF_4#
Low/Low for NB3W1200L
5 Output Enable DIF 5
Hi−Z for NB3N1200K
Enabled RW 1 DIF_5,
DIF_5#
Low/Low for NB3W1200L
6 Output Enable DIF 6
Hi−Z for NB3N1200K
Enabled RW 1 DIF_6,
DIF_6#
Low/Low for NB3W1200L
7 Output Enable DIF 7
Hi−Z for NB3N1200K
Enabled RW 1 DIF_7,
DIF_7#
Low/Low for NB3W1200L
Table 23. BYTE 2: OUTPUT ENABLE CONTROL REGISTER
Bit Description
If Bit = 0
If Bit = 1 Type Default
Output(s)
Affected
0 Output Enable DIF 8
Hi−Z for NB3N1200K
Enabled RW 1 DIF_8,
DIF_8#
Low/Low for NB3W1200L
1 Output Enable DIF 9
Hi−Z for NB3N1200K
Enabled RW 1 DIF_9,
DIF_9#
Low/Low for NB3W1200L
2
Output Enable DIF 10 Hi−Z for NB3N1200K
Enabled RW 1 DIF_10,
DIF_10#
Low/Low for NB3W1200L
3 Output Enable DIF 11
Hi−Z for NB3N1200K
Enabled RW 1 DIF_11,
DIF_11#
Low/Low for NB3W1200L
4 Reserved
5 Reserved
6 Reserved
7 Reserved

NB3N1200KMNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V 100/133MHz Diff 1:12 HCSL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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