NB3N1200K, NB3W1200L
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17
PWRDN# Assertion
When PWRDN# is sampled low by two consecutive rising edges of DIF#, all differential outputs must held tri-stated on the
next DIF# high to low transition.
Figure 10. PWRDN#—Assertion
DIF
DIF#
PWRDN#
PWRGD Assertion
The power−up latency is to be less than 1.8 ms. This is the
time from the valid CLK_IN input clocks and the assertion
of the PWRGD signal to the time that stable clocks are
output from the buffer chip (PLL locked). All differential
outputs stopped in a tri−state condition resulting from power
down must be driven high in less than 300 ms of PWRDN#
de−assertion to a voltage greater than 200 mV.
Figure 11. PWRGD Assertion (Pwrdown − De−assertion)
PWRGD
DIF
Tdrive_PWRDN#
<300 ms; >200 mV
Tstable
<1.8 mS
DIF#
HBW_BYPASS_LBW#
The HBW_BYPASS_LBW# is a tri level function input
pin (refer to Table 13 for VIL_Tri, VIM_Tri,
VIH_Tri−signal level). It is used to select between PLL high
bandwidth, bypass mode and PLL low bandwidth mode. In
the bypass mode, the input clock is passed directly to the
output stage which may result in up to 50 ps of additive
cycle−to−cycle jitter (50 ps + input jitter) on DIF outputs. In
the case of PLL mode, the input clock is passed through a
PLL to reduce high frequency jitter. The PLL HBW,
BYPASS, and PLL LBW mode may be selected by asserting
the HBW_BYPASS_LBW# input pin to the appropriate
level per the following table:
Table 19. PLL BANDWIDTH AND READBACK TABLE
HBW_BYPASS_LBW#
Pin
Mode
Byte 0,
Bit 7
Byte 0,
Bit 6
L LBW 0 0
M BYPASS 0 1
H HBW 1 1
Additionally, the NB3N1200K/NB3W1200L has the
ability to override the Latch value of the PLL operating
mode from hardware strap pin 5 via use of Byte 0, bits 2 and
1. Byte 0 Bit 3 must be set to 1 to allow user to change Bits
2 and 1 to affect the PLL. Bits 7 and 6 will always read back
the original latched value. A warm reset of the system will
have to be accomplished if the user changes these bits.
