NB3N1200K, NB3W1200L
www.onsemi.com
24
Table 30. DIF CLOCK OUTPUT CURRENT
Board Target Trace/Term Z Reference R, I
ref
= V
DD
/(3*R
r
) Output Current V
OH
@ Z
100 W R
REF
= 475 W 1%, I
ref
= 2.32 mA
I
OH
= 6*I
ref
0.7 V @ 50 W
85 W R
REF
= 412 W, 1%, I
ref
= 2.67 mA
I
OH
= 6*I
ref
0.7 V @ 43.2 W
NMOS Push−Pull Buffer Specifications for NB3W1200L
Low Power NMOS Push−Pull Differential Buffer
The NB3W1200L utilizes the low−power output buffer
for all differential clocks. This buffer uses efficient NMOS
push−pull drivers powered off a low voltage rail, offering a
reduction in power consumption, improved edge rate
performance, and cross point voltage control.
Figure 17. NMOS Push−Pull Buffer Diagram
Clock
Rs
Rs
Source Terminated
2 pF
2 pF
Receiver
3.3 V
Core
3.3 V
0.8 V Nominal
Zo = 20
ohms
Clock#
T−Line 10″ Typical
T−Line 10″ Typical
Power Filtering Example
Ferrite Bead Power Filtering
Recommended ferrite bead filtering equivalent to the following:
600 W impedance at 100 MHz, ≤ 0.1 W DCR max., ≥ 400 mA current rating.
Figure 18. Schematic Example of the NB3N1200K / NB3W1200L Power Filtering
Place at pin
FERRITE
FB1
V3P3
C1
10 mF
C10
1 mF
C9
1 mF
2.2
R1
VDDA
VDDR
2.2
R2
C7
0.1 mF
C8
0.1 mF
VDD_DIFF
VDD_DIFF
C2
0.1 mF
C4
0.1 mF
C3
0.1 mF
C5
0.1 mF
C5
0.1 mF
C5
0.1 mF
C5
0.1 mF
VDD for PLL
VDD for Input Receiver
