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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
Programmable output synthesizer generates clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
Digital Phase Locked-Loop (DPLL) provides all the
features necessary for generating SONET/SDH
compliant clocks including automatic hitless
reference switching, automatic mode selection
(locked, free-run, holdover), and selectable loop
bandwidth
Provides 3 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
Provides 3 sync inputs for output frame pulse
alignment
Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
Configurable input to output delay, and output to
output phase alignment
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Supports IEEE 1149.1 JTAG Boundary Scan
May 2006
Figure 1 - Block Diagram
dpll_mod_sel
tck tdotdi tmstrst_b
dpll_holdover
dpll_lock
sck
so
si
DPLL
rst_bcs_b
diff_en
Reference
Monitors
ref
sync
ref0
ref1
ref2
sync0
sync1
sync2
int_b
sdh_clk
sdh_fp
p_clk
p_fp
ref2:0
sync2:0
ref_&_sync_status
Controller &
State Machine
SPI Interface
SONET/SDH
APLL
diff_clk_p/n
IEEE 1449.1
JTAG
Master
Clock
osco
osci
sdh_filter filter_ref0 filter_ref1
Programmable
Synthesizer
ZL30122
SONET/SDH
Low Jitter Line Card Synchronizer
Data Sheet
Ordering Information
ZL30122GGG 64 Pin CABGA Trays
ZL30122GGG2 64 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
ZL30122 Data Sheet
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Zarlink Semiconductor Inc.
Applications
AMCs for AdvancedTCA
TM
and MicroTCA Systems
Multi-Service Edge Switches or Routers
DSLAM Line Cards
WAN Line Cards
RNC/Mobile Switching Center Line Cards
ADM Line Cards
ZL30122 Data Sheet
Table of Contents
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Zarlink Semiconductor Inc.
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 DPLL Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ZL30122GGG2

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free SONET/SDH PLL Line Card Synch.
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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