ZL30122 Data Sheet
7
Zarlink Semiconductor Inc.
Status
E1 dpll_lock O Lock Indicator (LVCMOS). This is the lock indicator pin for the DPLL. This
output goes high when the DPLL’s output is frequency and phase locked to the
input reference.
H1 dpll_holdover O Holdover Indicator (LVCMOS). This pin goes high when the DPLL enters the
holdover mode.
Serial Interface
C1 sck I Clock for Serial Interface (LVCMOS). Serial interface clock.
D2 si I Serial Interface Input (LVCMOS). Serial interface data input pin.
D1 so O Serial Interface Output (LVCMOS). Serial interface data output pin.
C2 cs_b I
u
Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This
pin is internally pulled up to Vdd.
E2 int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pulled up to VDD.
APLL Loop Filter
A5 sdh_filter A External Analog PLL Loop Filter terminal.
B5 filter_ref0 A Analog PLL External Loop Filter Reference.
C5 filter_ref1 A Analog PLL External Loop Filter Reference.
JTAG and Test
G4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
G2 tdi I
u
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it
should be left unconnected.
G3 trst_b I
u
Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
H3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
F2 tms I
u
Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
DD
. If this pin is not used
then it should be left unconnected.
Master Clock
H4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz
reference from a clock oscillator (XO, XTAL). The stability and accuracy of the
clock at this input determines the free-run accuracy and the long term holdover
stability of the output clocks.
Pin # Name
I/O
Type
Description
