ZL30122GGG2 Datasheet ZL30122GGG2, ZL30122GGG | P10-P12

ZL30122 Data Sheet

Zarlink Semiconductor Inc.

1.2 DPLL Mode Of Operation

The DPLL supports three modes of operation - free-run, normal, and holdover. The mode of operation can be

manually set or controlled by an automatic state machine as shown in Figure 2.

Figure 2 - Automatic Mode State Machine

Free-run

The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a

reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the

external master oscillator.

Lock Acquisition

The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the

input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given

a stable reference input, the ZL30122 will enter in the Normal (locked) mode.

Normal (locked)

The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified

reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency

accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with

the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication

standards.

Holdover

When the DPLL operating in the normal mode loses its reference input, and no other qualified references are

available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data

collected while the DPLL was synchronized. The transition between normal and holdover modes is controlled by

the DPLL so that its initial frequency offset is better than 100 ppb. The frequency drift after this transition period is

dependant on the frequency drift of the external master oscillator.

Reset

Another reference is

qualified and available

for selection

Phase lock on

the selected

reference is

achieved

Lock

Acquisition

Normal

(Locked)

No references are

qualified and

available for

selection

Free-Run

Holdover

Selected reference

fails

All references are monitored

for frequency accuracy and

phase regularity, and at least

one reference is qualified.

Normal

(Locked)

ZL30122 Data Sheet

Zarlink Semiconductor Inc.

1.3 Ref and Sync Inputs

There are three reference clock inputs (ref0 to ref2) available to the DPLL. Reference selection can be controlled

using a built-in state machine or set in a manual mode.The selected reference input is used to synchronize the

output clocks.

Figure 3 - Reference and Sync Inputs

In addition to the reference inputs, the DPLL has three optional frame pulse synchronization inputs (sync0 to

sync2) used to align the output frame pulses. The sync

input is selected with its corresponding ref

input, where n

= 0, 1, or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of

the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.

Figure 4 - Output Frame Pulse Alignment

ref2:0

sync2:0

DPLL

ref

diff_clk/sdh_clk/p_clk

sdh/p_fp

Without a frame pulse

signal at the sync input,

the output frame pulses

will align to any arbitrary

cycle of its associated

output clock.

sync

- no frame pulse signal present

When a frame pulse

signal is present at the

sync input, the DPLL

will align the output

frame pulses to the

output clock edge that is

aligned to the input

frame pulse.

ref

sync

n = 0, 1, 2

diff_clk/sdh_clk/p_clk

sdh_fp/p_fp

ZL30122 Data Sheet

Zarlink Semiconductor Inc.

Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz.

Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is

within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz

are also available.

Each of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising

edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width

requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies

shown in Table 3.

1.4 Ref and Sync Monitoring

All input references (ref0 to ref2) are monitored for frequency accuracy and phase regularity. New references are

qualified before they can be selected as a synchronization source, and qualified references are continuously

monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on

four levels of monitoring.

Single Cycle Monitor (SCM)

The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock

edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure

(scm_fail) is declared.

2 kHz

8 kHz

64 kHz

1.544 MHz

2.048 MHz

6.48 MHz

8.192 MHz

16.384 MHz

19.44 MHz

38.88 MHz

77.76 MHz

Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies

166.67 Hz

(48x 125 μs frames)

400 Hz

1 kHz

2 kHz

8 kHz

64 kHz

Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

ZL30122GGG2

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Clock Generators & Support Products Pb Free SONET/SDH PLL Line Card Synch.

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ZL30122GGG2

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