ZL30122 Data Sheet
19
Zarlink Semiconductor Inc.
54 Reserved Leave as default
55 sdh_offset_fine 00 Control register for the output/output phase
alignrment fine tuning for sdh path
R/W
56 sdh_fp_freq 05 Control register to select the sdh_fp frame
pulse frequency
R/W
57 sdh_fp_type 23 Control register to select sdh_fp type R/W
58 sdh_fp_fine_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
59 sdh_fp_fine_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5A sdh_fp_coarse_offset 00 Programmable frame pulse phase offset in
multiples of 8 kHz cycles
R/W
5B -
5F
Reserved Leave as default
Differential Output Configuration
60 diff_clk_ctrl A3 Control register to enable diff_clk R/W
61 diff_clk_sel 53 Control register to select the diff_clk frequency R/W
External Feedback Configuration
62 Reserved Leave as default
63 fb_offset_fine F5 Control register for the output/output phase
alignment fine tuning
R/W
64 reserved
Custom Input Frequencies
65 ref_freq_mode_0 00 Control register to set whether to use auto
detect, CustomA or CustomB for ref0 to ref2
R/W
66 Reserved Leave as default
67 custA_mult_0 00 Control register for the [7:0] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
68 custA_mult_1 00 Control register for the [13:8] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
69 custA_scm_low 00 Control register for the custom configuration A:
single cycle SCM low limiter
R/W
6A custA_scm_high 00 Control register for the custom configuration
A: single cycle SCM high limiter
R/W
6B custA_cfm_low_0 00 Control register for the custom configuration
A: The [7:0] bits of the single cycle CFM low
limit
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
