ZL30122GGG2 Datasheet ZL30122GGG2, ZL30122GGG | P13-P15

ZL30122 Data Sheet

Zarlink Semiconductor Inc.

Coarse Frequency Monitor (CFM)

The CFM block monitors the reference frequency over a measurement period of 30 μs so that it can quickly detect

large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by more than 3%

or approximately 30000 ppm.

Precise Frequency Monitor (PFM)

The PFM block measures the frequency accuracy of the reference over a 10 second interval. To ensure an

accurate frequency measurement, the PFM measurement interval is re-initiated if phase or frequency irregularities

are detected by the SCM or CFM. The PFM provides a level of hysteresis between the acceptance range and the

rejection range to prevent a failure indication from toggling between valid and invalid for references that are on the

edge of the acceptance range.

When determining the frequency accuracy of the reference input, the PFM uses the external oscillator’s output

frequency (f

ocsi

) as its point of reference.

Guard Soak Timer (GST)

The GST block mimics the operation of an analog integrator by accumulating failure events from the CFM and the

SCM blocks and applying a selectable rate of decay when no failures are detected.

As shown in Figure 5, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper

threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator

decrements until it reaches its lower threshold during the qualification window.

Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures

Sync Ratio Monitor

All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference

clock cycles within the frame pulse period.

ref

CFM or SCM failures

upper threshold

lower threshold

- disqualification time

- qualification time = n * t

gst_fail

ZL30122 Data Sheet

Zarlink Semiconductor Inc.

1.5 Output Clocks and Frame Pulses

The ZL30122 offers a wide variety of outputs including one low-jitter differential LVPECL clock (diff_clk_p/n), one

SONET/SDH LVCMOS (sdh_clk) output clock and one programmable LVCMOS (p_clk) output clock. In addition to

the clock outputs, one LVCMOS SONET/SDH frame pulse output (sdh_fp) and one LVCMOS programmable frame

pulse (p_fp) is also available.

Figure 6 - Output Configuration

The supported frequencies for the output clocks and frame pulses are shown in Table 4.

diff_clk_p/n

(LVPECL)

sdh_clk

(LVCMOS)

p_clk

(LVCMOS)

sdh_fp, p_fp

(LVCMOS)

6.48 MHz 6.48 MHz 2 kHz 166.67 Hz

(48x 125 μs frames)

19.44 MHz 9.72 MHz N * 8 kHz (up to 77.76

MHz)

400 Hz

38.88 MHz 12.96 MHz 1 kHz

51.84 MHz 19.44 MHz 2 kHz

77.76 MHz 25.92 MHz 4 kHz

155.52 MHz 38.88 MHz 8 kHz

311.04 MHz 51.84 MHz 32 kHz

622.08 MHz 77.76 MHz 64 kHz

Table 4 - Output Clock and Frame Pulse Frequencies

DPLL

p_clk

p_fp

Programmable

Synthesizer

sdh_clk

sdh_fp

SONET/SDH

APLL

diff_clk_p/n

ZL30122 Data Sheet

Zarlink Semiconductor Inc.

1.6 Configurable Input-to-Output and Output-to-Output Delays

The ZL30122 allows programmable static delay compensation for controlling input-to-output and output-to-output

delays of its clocks and frame pulses.

Both the SONET/SDH APLL and the Programmable Synthesizer can be configured to lead or lag the selected input

reference clock using the DPLL Fine Delay. The delay is programmed in steps of 119.2 ps with a range of -128 to

+127 steps giving a total delay adjustment in the range of -15.26 ns to +15.14 ns. Negative values delay the output

clock, positive values advance the output clock.

In addition to the delay introduced by the DPLL Fine Delay, the SONET/SDH APLL and programmable synthesizer

have the ability to add their own fine delay adjustments using the P Fine Delay and SDH Fine Delay. These delays

are also programmable in steps of 119.2 ps with a range of -128 to +127 steps.

In addition to these delays, the single-ended output clocks of the SONET/SDH and Programmable synthesizers

can be independently offset by 90, 180 and 270 degrees using the Coarse Delay, and the SONET/SDH differential

outputs can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the Diff Delay. The output frame

pulses (sdh_clk, p_fp) can be independently offset with respect to each other using the FP Delay.

Figure 7 - Phase Delay Adjustments

DPLL

P Fine Delay

p_clk

p_fp

Programmable

Synthesizer

Coarse Delay

FP Delay

Diff Delay

diff_clk_p/n

SONET/SDH

APLL

sdh_clk

sdh_fp

SDH Fine Delay

Coarse Delay

FP Delay

DPLL Fine Delay

Feedback

Synthesizer

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ZL30122GGG2

Mfr. #:

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Manufacturer:

Microchip / Microsemi

Description:

Clock Generators & Support Products Pb Free SONET/SDH PLL Line Card Synch.

Lifecycle:

New from this manufacturer.

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ZL30122GGG2

ZL30122GGG2

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