ZL30122 Data Sheet
17
Zarlink Semiconductor Inc.
14 detected_sync_0 EE Sync0 and sync1 auto-detected frequency
value and sync failure status register
R
15 detected_sync_1 0E Sync2 auto-detected frequency value and sync
valid status register
R
16 oor_ctrl_0 33 Control register for the ref0 and ref1 out of
range limit
R/W
17 oor_ctrl_1 33 Control register for the ref2 out of range limit R/W
18 Reserved Leave as default
19 Reserved Leave as default
1A gst_mask FF Control register to mask the inputs to the guard
soak timer for ref0 - ref2
R/W
1B Reserved Leave as default
1C gst_qualif_time 1A Control register for the guard_soak_timer
qualification time and disqualification time for
the references
R/W
DPLL Control
1D dpll_ctrl_0 See
Register
Description
Control register for the DPLL filter control;
phase slope limit, bandwidth and hitless
switching
R/W
1E dpll_ctrl_1 See
Register
Description
Holdover update time, filter_out_en,
freq_offset_en, revert enable
R/W
1F dpll_modesel See
Register
Description
Control register for the DPLL mode of
operation
R/W
20 dpll_refsel 00 DPLL reference selection or reference selection
status
R/W
21 dpll_ref_fail_mask 3C Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
R/W
22 dpll_wait_to_restore 00 Control register to indicate the time to restore a
previous failed reference
R/W
23 dpll_ref_rev_ctrl 00 Control register for the ref0 to ref2 enable
revertive signals
R/W
24 dpll_ref_pri_ctrl_0 10 Control register for the ref0 and ref1 priority
values
R/W
25 dpll_ref_pri_ctrl_1 32 Control register for the ref2 priority values R/W
26 Reserved Leave as default
27 Reserved Leave as default
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
