Data Sheet AD1934
Rev. D | Page 15 of 28
Table 12. Pin Function Changes in TDM and AUX Modes
Pin Name Stereo Modes TDM Modes AUX Modes
AUXDATA1 Not Used (Float) Not Used (Float) AUX Data Out 1 (to External DAC 1)
DSDATA1 DAC1 Data In DAC TDM Data In TDM Data In
DSDATA2 DAC2 Data In DAC TDM Data Out Not Used (Ground)
DSDATA3 DAC3 Data In DAC TDM Data In 2 (Dual-Line Mode) Not Used (Ground)
DSDATA4 DAC4 Data In DAC TDM Data Out 2 (Dual-Line Mode) AUX Data Out 2 (to External DAC 2)
AUXTDMLRCLK Not Used (Ground) Not Used (Ground) TDM Frame Sync In/Out
AUXTDMBCLK Not Used (Ground) Not Used (Ground) TDM BCLK In/Out
DLRCLK DAC LRCLK In/Out DAC TDM Frame Sync In/Out AUX LRCLK In/Out
DBCLK DAC BCLK In/Out DAC TDM BCLK In/Out AUX BCLK In/Out
LEFT RIGHT
MSB MSB
MSB MSB
AUXTDMLRCLK
AUXTDMBCLK
DSDATA1
(TDM_IN)
DLRCLK
(AUX PORT)
DBCLK
(AUX PORT)
AUXDATA1
(AUX1_OUT)
DSDATA4
(AUX2_OUT)
MSB
EMPTY EMPTY EMPTY EMPTY DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2
8-ON-CHIP DAC CHANNELS
AUXILIARY DAC CHANNELS
WILL APPEAR AT
AUX DAC PORTSUNUSED SLOTS
32 BITS
0
6106-051
Figure 11. 16-Channel DAC TDM-AUX Mode
AD1934 Data Sheet
Rev. D | Page 16 of 28
DAISY-CHAIN MODE
The AD1934 also allows a daisy-chain configuration to expand
the system 16 DACs (see Figure 12). In this mode, the DBCLK
frequency is 512 f
S
. The first eight slots of the DAC TDM data
stream belong to the first AD1934 in the chain and the last eight
slots belong to the second AD1934. The second AD1934 is the
device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1934 can be configured into a dual-line, DAC TDM mode,
as shown in Figure 13. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1934 in the chain and the last four channels belong to
the second AD1934.
The dual-line, DAC TDM mode can also be used to send data at
a 192 kHz sample rate into the AD1934, as shown in Figure 14.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 13 for a detailed description of
the function of each pin. See Figure 18 for a typical AD1934
configuration with two external stereo DACs. Figure 15 and
Figure 16 show the serial mode formats. For maximum
flexibility, the polarity of LRCLK and BCLK are programmable.
In these figures, all of the clocks are shown with their normal
polarity. The default mode is I
2
S.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
DSDATA1 (TDM_IN)
OF THE SECOND AD1934
DSDATA2 (TDM_OUT)
OF THE SECOND AD1934
THIS IS THE TDM
TO THE FIRST AD1934
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD1934
FIRST
AD1934
06106-054
Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain)
DLRCLK
DBCLK
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(IN)
DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2
DSDATA3
(IN)
DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4
DSDATA2
(OUT)
DAC L1 DAC R1 DAC L2 DAC R2
DSDATA4
(OUT)
DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD1934
FIRST
AD1934
MSB
06106-055
Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain; DSDATA3 and DSDATA4 Are the Daisy Chain)
Data Sheet AD1934
Rev. D | Page 17 of 28
06106-058
DLRCLK
DBCLK
DSDATA1
DAC L1 DAC R1 DAC L2 DAC R2
DSDATA2
DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
MSB
Figure 14. Dual-Line, DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LSB LSB
LSB
LSB
LSB LSB
LEFT CHANNEL RIGHT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LEFT CHANNEL RIGHT CHANNEL
MSB MSB
MSB
MSB
MSB MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I
2
S MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDAT
A
LSB LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
f
S
EXCEPT FOR DSP MODE, WHICH IS 2 ×
f
S
.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB MSB
1/
f
S
06106-013
Figure 15. Stereo Serial Modes

AD1934YSTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Audio D/A Converter ICs IC 8 CHAudio w/on chip PLL
Lifecycle:
New from this manufacturer.
Delivery:
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