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AD1934YSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
AD1934 Data Sheet
Rev. D | Page 6 of 28
DIGITAL FILTERS
Table 6.
Parameter Mode Factor Min Typ Max Unit
DAC INTERPOLATION FILTER
Pass Band 48 kHz mode, typ @ 48 kHz 0.4535 f
S
22 kHz
96 kHz mode, typ @ 96 kHz 0.3646 f
S
35 kHz
192 kHz mode, typ @ 192 kHz 0.3646 f
S
70 kHz
Pass-Band Ripple 48 kHz mode, typ @ 48 kHz ±0.01 dB
96 kHz mode, typ @ 96 kHz
±0.05
dB
192 kHz mode, typ @ 192 kHz ±0.1 dB
Transition Band 48 kHz mode, typ @ 48 kHz 0.5 f
S
24 kHz
96 kHz mode, typ @ 96 kHz 0.5 f
S
48 kHz
192 kHz mode, typ @ 192 kHz 0.5 f
S
96 kHz
Stop Band 48 kHz mode, typ @ 48 kHz 0.5465 f
S
26 kHz
96 kHz mode, typ @ 96 kHz 0.6354 f
S
61 kHz
192 kHz mode, typ @ 192 kHz 0.6354 f
S
122 kHz
Stop-Band Attenuation 48 kHz mode, typ @ 48 kHz 70 dB
96 kHz mode, typ @ 96 kHz 70 dB
192 kHz mode, typ @ 192 kHz 70 dB
Group Delay
48 kHz mode, typ @ 48 kHz
25/f
S
521
µs
96 kHz mode, typ @ 96 kHz 11/f
S
115 µs
192 kHz mode, typ @ 192 kHz 8/f
S
42 µs
TIMING SPECIFICATIONS
−40°C < T
C
< 125°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET
t
MH
MCLK duty cycle DAC clock source = PLL clock @ 256 f
S
,
384 f
S
, 512 f
S
, 768 f
S
40 60 %
t
MH
DAC clock source = direct MCLK @ 512 f
S
(bypass on-chip PLL)
40
60
%
f
MCLK
MCLK frequency PLL mode, 256 f
S
reference 6.9 13.8 MHz
f
MCLK
Direct 512 f
S
mode 27.6 MHz
t
PDR
RST
low 15 ns
t
PDRR
RST
recovery Reset to active output 4096 t
MCLK
PLL
Lock Time MCLK and LRCLK input 10 ms
256 f
S
VCO Clock, Output Duty Cycle
MCLKO Pin
40 60 %
SPI PORT See Figure 9
t
CCH
CCLK high
35
ns
t
CCL
CCLK low 35 ns
f
CCLK
CCLK frequency f
CCLK
= 1/t
CCP
, only t
CCP
shown in Figure 9 10 MHz
t
CDS
CDATA setup To CCLK rising 10 ns
t
CDH
CDATA hold From CCLK rising 10 ns
t
CLS
CLATCH
setup To CCLK rising 10 ns
t
CLH
CLATCH
hold
From CCLK rising
10
ns
t
CLHIGH
CLATCH
high Not shown in Figure 9 10 ns
t
COE
COUT enable From CCLK falling 30 ns
t
COD
COUT delay From CCLK falling 30 ns
t
COH
COUT hold From CCLK falling, not shown in Figure 9 30 ns
t
COTS
COUT tri-state From CCLK falling 30 ns
Data Sheet AD1934
Rev. D | Page 7 of 28
Parameter Condition Comments Min Max Unit
DAC SERIAL PORT See Figure 16
t
DBH
DBCLK high Slave mode 10 ns
t
DBL
DBCLK low Slave mode 10 ns
t
DLS
DLRCLK setup To DBCLK rising, slave mode 10 ns
t
DLH
DLRCLK hold
From DBCLK rising, slave mode
5
ns
t
DLS
DLRCLK skew From DBCLK falling, master mode −8 +8 ns
t
DDS
DSDATA setup To DBCLK rising 10 ns
t
DDH
DSDATA hold From DBCLK rising 5 ns
AUXTDM SERIAL PORT See Figure 17
t
ABH
AUXTDMBCLK high Slave mode 10 ns
t
ABL
AUXTDMBCLK low Slave mode 10 ns
t
ALS
AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns
t
ALH
AUXTDMLRCLK hold From AUXTDMBCLK rising, slave mode 5 ns
t
ALS
AUXTDMLRCLK skew
From AUXTDMBCLK falling, master mode
−8
+8
ns
t
DDS
DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns
t
DDH
DSDATA hold From AUXTDMBCLK rising, not shown in
Figure 17
5 ns
AUXILIARY INTERFACE
t
DXDD
AUXDATA delay From AUXBCLK falling 18 ns
t
XBH
AUXBCLK high 10 ns
t
XBL
AUXBCLK low 10 ns
t
DLS
AUXLRCLK setup
To AUXBCLK rising
10
ns
t
DLH
AUXLRCLK hold From AUXBCLK rising 5 ns
AD1934 Data Sheet
Rev. D | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Rating
Analog (AVDD) −0.3 V to +3.6 V
Digital (DVDD) −0.3 V to +3.6 V
Input Current (Except Supply Pins) ±20 mA
Analog Input Voltage (Signal Pins) −0.3 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V
Operating Temperature Range (Case) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
represents thermal resistance, junction-to-ambient;
θ
JC
represents the thermal resistance, junction-to-case.
All characteristics are for a 4-layer board.
Table 9. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
48-Lead LQFP 50.1 17 °C/W
ESD CAUTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

AD1934YSTZ

Mfr. #:
Buy AD1934YSTZ
Manufacturer:
Analog Devices Inc.
Description:
Audio D/A Converter ICs IC 8 CHAudio w/on chip PLL
Lifecycle:
New from this manufacturer.
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