Data Sheet AD1934
Rev. D | Page 23 of 28
AUXILIARY TDM PORT CONTROL REGISTERS
Table 23. Auxiliary TDM Control 0
Bit Value Function Description
1:0 00 24 Word width
01 20
10 Reserved
11 16
4:2 000 1 SDATA delay (BCLK periods)
001 0
010 8
011 12
101 Reserved
110 Reserved
111 Reserved
6:5 00 Reserved Serial format
01 Reserved
10 DAC aux mode
11 Reserved
7 0 Latch in midcycle (normal) BCLK active edge (TDM in)
1 Latch in at end of cycle (pipeline)
Table 24. Auxiliary TDM Control 1
Bit Value Function Description
0 0 50/50 (allows 32/24/20/16 BCLK/channel) LRCLK format
1 Pulse (32 BCLK/channel)
1 0 Drive out on falling edge (DEF) BCLK polarity
1 Drive out on rising edge
2 0 Left low LRCLK polarity
1 Left high
3 0 Slave LRCLK master/slave
1 Master
5:4 00 64 BCLKs per frame
01 128
10 256
11 512
6 0 Slave BCLK master/slave
1 Master
7 0 AUXTDMBCLK pin BCLK source
1 Internally generated
ADDITIONAL MODES
The AD1934 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 19 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configuration
is applicable when the AD1934 master clock is generated by the
PLL with the DLRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the AD1934 in
cases of high speed TDM data transmission, the AD1934 can
latch in the data using the falling edge of DBCLK. This
effectively dedicates the entire BCLK period to the setup time.
This mode is useful in cases where the source has a large delay
time in the serial data driver. Figure 20 shows this pipeline
mode of data transmission.
Both the BLCK-less and pipeline modes are available.
