Operating features M95M01-R M95M01-W
14/41 Doc ID 13264 Rev 8
4.4 Status Register
Figure 7 shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits
4.5 Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
● Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Write (WRITE) instruction completion
● The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
● The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S
) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
● The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
● The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-protected block size
Status Register bits
Protected block
Array addresses
protected
BP1 BP0
0 0 none none
0 1 Upper quarter 1 8000h - 1 FFFFh
1 0 Upper half 1 0000h - 1 FFFFh
1 1 Whole memory 0 0000h - 1 FFFFh
