Instructions M95M01-R M95M01-W
24/41 Doc ID 13264 Rev 8
6.6 Write to Memory Array (WRITE)
As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S
) high at a byte boundary of the input
data. In the case of Figure 13, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts, and continues for a period t
WC
(as specified in Ta bl e 15 ), at the end of
which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S
) continues to be driven low, as shown in Figure 14, the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle. The self-
timed Write cycle starts, and continues, for a period t
WC
(as specified in Ta bl e 1 5), at the
end of which the Write in Progress (WIP) bit is reset to 0.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size is 256 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
● if a Write cycle is already in progress
● if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note: The self-timed write cycle, t
W
, is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 13. Byte Write (WRITE) sequence
1. As shown in Table 6, the most significant address bits are Don’t Care.
C
D
AI13879
S
Q
23
21 345678910 2829303132333435
1413 3210
36 37 38
High Impedance
Instruction 24-bit address
0
765432 0
1
Data byte
39
