ECC (error correction code) and write cycling M95M01-R M95M01-W
26/41 Doc ID 13264 Rev 8
7 ECC (error correction code) and write cycling
The M95M01-R and M95M01-W devices offer an ECC (error correction code) logic which
compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a
single bit out of 4 bytes of data happens to be erroneous during a read operation, the ECC
detects it and replaces it by the correct value. The read reliability is therefore much improved
by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write by words of 4 bytes in order to
benefit from the larger amount of Write cycles.
The M95M01-R and M95M01-W devices are qualified at 1 million (1 000 000) write cycles,
using a cycling routine that writes to the device by multiples of 4-byte packets.
8 Power-up and delivery state
8.1 Power-up state
After power-up, the device is in the following state:
● Standby Power mode
● Deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
● Not in the Hold condition
● Write Enable Latch (WEL) is reset to 0
● Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
8.2 Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
