DC and AC parameters M95M01-R M95M01-W
32/41 Doc ID 13264 Rev 8
Table 15. AC characteristics (M95M01-R6, V
CC
< 2.5 V)
Test conditions specified in Tabl e 8 and Tabl e 10
Symbol Alt. Parameter Min. Max. Min.
(1)
Max.
(1)
Unit
f
C
f
SCK
Clock frequency D.C. 2 D.C. 5 MHz
t
SLCH
t
CSS1
S active setup time 150 60 ns
t
SHCH
t
CSS2
S not active setup time 150 60 ns
t
SHSL
t
CS
S deselect time 200 90 ns
t
CHSH
t
CSH
S active hold time 150 60 ns
t
CHSL
S not active hold time 150 60 ns
t
CH
(2)
t
CLH
Clock high time 200 80 ns
t
CL
(2)
t
CLL
Clock low time 200 80 ns
t
CLCH
(3)
t
RC
Clock rise time 2 µs
t
CHCL
(3)
t
FC
Clock fall time 2 µs
t
DVCH
t
DSU
Data in setup time 50 20 ns
t
CHDX
t
DH
Data in hold time 50 20 ns
t
HHCH
Clock low hold time after HOLD not active 150 60 ns
t
HLCH
Clock low hold time after HOLD active 150 60 ns
t
CLHL
Clock low setup time before HOLD active 0 0 ns
t
CLHH
Clock low setup time before HOLD not active 0 0 ns
t
SHQZ
(3)
t
DIS
Output Disable time 200 80 ns
t
CLQV
(4)
t
V
Clock low to output valid 200 80 ns
t
CLQX
t
HO
Output hold time 0 0 ns
t
QLQH
(3)
t
RO
Output rise time 200 80 ns
t
QHQL
(3)
t
FO
Output fall time 200 80 ns
t
HHQV
t
LZ
HOLD high to output valid 200 80 ns
t
HLQZ
(3)
t
HZ
HOLD low to output high-Z 200 80 ns
t
W
t
WC
Write time 5 5 ms
1. For devices identified with process letter K.
2. t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max)
3. Value guaranteed by characterization, not 100% tested in production.
4. t
CLQV
must be compatible with t
CL
(clock low time): if the SPI bus master offers a read setup time t
SU
= 0 ns, t
CL
can be
equal to (or greater than) t
CLQV
; in all other cases, t
CL
must be equal to (or greater than) t
CLQV
+t
SU
.
