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1894K-33LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
ICS1894-33
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 10
ICS1894-33 REV A 021612
Receive Error (RX_ER)
RX_ER is asserted for one or more REFIN periods to
indicate that an error (e.g. a coding error or any error that a
PHY is capable of detecting, and that may otherwise be
undetectable by the MAC sub-layer) was detected
somewhere in the frame presently being transferred from
the PHY. RX_ER transitions synchronously with respect to
REFIN. While CRS_DV is de-asserted, RX_ER has no
effect on the MAC.
Auto-MDI/MDIX Crossover
The ICS1894-33 includes the auto-MDI/MDIX crossover
feature. In a typical CAT 5 Ethernet installation the transmit
twisted pair signal pins of the RJ45 connector are crossed
over in the CAT 5 wiring to the partners receive twisted pair
signal pins and receive twisted pair to the partners transmit
twisted pair. This is usually accomplished in the wiring plant.
Hubs generally wire the RJ45 connector crossed to
accomplish the crossover. Two types of CAT 5 cables
(straight and crossed) are available to achieve the correct
connection. The Auto-MDI/MDIX feature automatically
corrects for miss-wired installations by automatically
swapping transmit and receive signal pairs at the PHY when
no link results. Auto-MDI/MDIX is automatic, but may be
disabled for test purposes by writing MDIO register 19 Bits
9:8 in the MDIO register. The Auto-MDI/MDIX function is
independent of Auto-Negotiation and preceeds
Auto-Negotiation when enabled.
Auto MDI/MDIX Table
Definitions:
straight transmit = TP_AP & TP_AN
receive = TP_BP & TP_BN
cross transmit = TP_BP & TP_BN
receive = TP_AP & TP_AN
AMDIX_EN (Pin 14) AMDIX enable pin with 20 kOhm
pull-up resistor
AMDIX_EN [19:9] MDIO register 19h bit 9
MDI_MODE [19:8] MDIO register 19h bit 8
AMDIX_EN
(pin 14)
AMDIX_EN
[Reg 19:9]
MDI_MODE
[Reg 19:8]
Tx/Rx MDI
Configuration
x 0 0 straight
x01 cross
0 1 x straight
1 1 x straight/cross (auto
select)
Default
1 1 0 straight/cross (auto
select)
ICS1894-33
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 11
ICS1894-33 REV A 021612
Power Management
The ICS1894-33 supports a Deep Power Mode (DPD) that
is enabled under the following conditions:
1. The Phy is not Receiving any signal from the partner (Link
Down)
2. The MAC is not transmitting data to the Phy (TXEN Low)
Once the above conditions are met, the Phy goes into DPD
mode after 32s (typical).
The logic internal to the device can be selectively shut down
in DPD mode depending on Register 24 Bits 8-4.
Block Diagram of the Different Sections of the PHY as Affected by Register 24 bits
Clock Reference Interface
The REFIN pin provides the ICS1894-33 Clock Reference
Interface. The ICS1894-33 requires a single clock reference
with a frequency of 25 MHz ±50 parts per million. This
accuracy is necessary to meet the interface requirements of
the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1
and 24.2.3.4. The ICS1894-33 supports two clock source
configurations: a CMOS oscillator or a CMOS driver. The
input to REFIN is CMOS (10% to 90% VDD), not TTL.
Alternately, a 25MHz crystal may be used.
TPLL
Controlled by Register 24.7
XMIT_DAC
Controlled
by Register
24.5
TX_STRUCTURE
If XMIT_DAC is
powered down,
this block is
High_Z
OUT IN
RX and
Equalizer
Controlled by
Register 24.6
CDR
Controlled by
Register 24.4
Reference Clock
10/100M Drive Clock
Bias Current
Bias for RxBias for 10/100M
BGAP
Vbg
ICS1894-33
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 12
ICS1894-33 REV A 021612
Crystal or Oscillator Connection
50 MHz Oscillator Specification table
Status Interface
The ICS1894-33 has two multi-function configuration pins
that report the PHY status by providing signals that are
intended for driving LEDs. Configuration is set by Bank0
Register 20.
10 pF (optional)
REFIN
30
REFOUT
29
CMOS
50.000
MHz
33 Ohm (optional)
NC
ICS1894-33
RMII w/ Oscillator Input
Specifications Symbol Minimum Typical Maximum Unit
Output Frequency F0 49.9975 50.00000 50.0025 MHz
Freq. Stability (including aging)
ΔF/f ± 50 ppm
Duty cycle CMOS level one-half VDD Tw/T 35 65 %
VIH 2.79 Volts
VIL 0.33 Volts
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

1894K-33LFT

Mfr. #:
Buy 1894K-33LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
Delivery:
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