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1894K-33LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
ICS1894-33
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 7
ICS1894-33 REV A 021612
Functional Description
The ICS1894-33 is an ethernet PHYceiver. During data
transmission, it accepts sequential nibbles/di-bits from the
MAC (Media Access Control), converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-33 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles/di-bits. It
subsequently presents these nibbles/di-bits to the MAC
Interface.
The ICS1894-33 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
• Physical Coding sublayer (PCS)
• Physical Medium Attachment sublayer (PMA)
• Physical Medium Dependent sublayer (PMD)
• Auto-Negotiation sublayer
The ICS1894-33 is transparent to the next layer of the OSI
model, the link layer. The link layer has two sublayers: the
Logical Link Control sublayer and the MAC sublayer. The
ICS1894-33 can interface directly with the MAC via RMII
interface signals.
TheICS1894-33 transmits framed packets acquired from its
MAC Interface and receives encapsulated packets from
another PHY, which it translates and presents to its MAC
Interface.
Note: As per the ISO/IEC standard, the
ICS1894-33 does not affect, nor is it
affected by, the underlying structure of the
MAC frame it is conveying.
100Base-TX Operation
During 100Base-TX data transmission, the ICS1894-33
accepts packets from the MAC and inserts Start-of-Stream
Delimiters (SSDs) and End-of-Stream Delimiters (ESDs)
into the data stream. The ICS1894-33 encapsulates each
MAC frame, including the preamble, with an SSD and an
ESD. As per the ISO/IEC Standard, the ICS1894-33
replaces the first octet of each MAC preamble with an SSD
and appends an ESD to the end of each MAC frame.
When receiving data from the medium, the ICS1894-33
removes each SSD and replaces it with the pre-defined
preamble pattern before presenting the data on the MAC
Interface. When the ICS1894-33 encounters an ESD in the
received data stream, signifying the end of the frame, it ends
the presentation of data on the MAC Interface. Therefore,
the local MAC receives an unaltered copy of the transmitted
frame sent by the remote MAC.
During periods when MAC frames are being neither
transmitted nor received, the ICS1894-33 signals and
detects the IDLE condition on the Link Segment. In the
100Base-TX mode, the ICS1894-33 transmit channel sends
a continuous stream of scrambled ones to signify the IDLE
condition. Similarly, the ICS1894-33 receive channel
continually monitors its data stream and looks for a pattern
of scrambled ones. The results of this signaling and
monitoring provide the ICS1894-33 with the means to
establish the integrity of the Link Segment between itself
and its remote link partner and inform its Station
Management Entity (SME) of the link status.
10Base-T Operation
During 10Base-T data transmission, the ICS1894-33 inserts
only the IDL delimiter into the data stream. The ICS1894-33
appends the IDL delimiter to the end of each MAC frame.
However, since the 10Base-T preamble already has a
Start-of-Frame delimiter (SFD), it is not required that the
ICS1894-33 insert an SSD-like delimiter.
When receiving data from the medium (such as a
twisted-pair cable), the ICS1894-33 uses the preamble to
synchronize its receive clock. When the ICS1894-33
receive clock establishes lock, it presents the preamble
nibbles to the MAC Interface.
In 10M operations, during periods when MAC frames are
being neither transmitted nor received, the ICS1894-33
signals and detects Normal Link Pulses. This action allows
the integrity of the Link Segment with the remote link partner
to be established and then reported to the ICS1894-33’s
SME.
Auto-Negotiation
The ICS1894-33 conforms to the auto-negotiation protocol,
defined in Clause 28 of the IEEE 802.3u specification.
Autonegotiation is enabled by either hardware pin strapping
(pin 20) or software (register 0h bit 12).
Auto-negotiation allows link partners to select the highest
common mode of operation. Link partners advertise their
capabilities to each other, and then compare their own
capabilities with those they received from their link partners.
The highest speed and duplex setting that is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation
mode from highest to lowest.
ICS1894-33
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 8
ICS1894-33 REV A 021612
• Priority 1: 100Base-TX, full-duplex
• Priority 2: 100Base-TX, half-duplex
• Priority 3: 10Base-T, full-duplex
• Priority 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the ICS1894-33 link
partner is forced to bypass auto-negotiation, the
ICS1894-33 sets its operating mode by observing the signal
at its receiver. This is known as parallel detection, and
allows the ICS1894-33 to establish link by listening for a
fixed signal protocol in the absence of auto-negotiation
advertisement protocol.
MII Management (MIIM) Interface
The ICS1894-33 supports the IEEE 802.3 MII Management
Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface allows upper-layer
devices to monitor and control the state of the ICS1894-33.
An external device with MIIM capability is used to read the
PHY status and/or configure the PHY settings. Additional
details on the MIIM interface can be found in Clause
22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line
(MDC) and the data line (MDIO).
• A specific protocol that operates across the
aforementioned physical connection that allows an
external controller to communicate with one or more
ICS1894-33 devices. Each ICS1894-33 device is
assigned a PHY address between 1 and 7 by the P[4:0]
strapping pins. P3 and P4 address bits are hardcoded to
‘0’ in design.
• An internal addressable set of thirty-one 8-bit MDIO
registers. Register [0:6] are required, and their functions
are defined by the IEEE 802.3u Specification. The
additional registers are provided for expanded
functionality.
The following table shows the MII Management frame
format for the ICS1894-33.
MII Management Frame Format
Interrupt (INT)
P2/INT (pin 11) is an optional interrupt signal that is used to
inform the external controller that there has been a status
update in the ICS1894-33 PHY register. Register 23 shows
the status of the various interrupts while register 22 controls
the enabling/disabling of the interrupts.
MII Data Interface
The Media Independent Interface (MII) is specified in
Clause 22 of the IEEE 802.3u Specification. It provides a
common interface between physical layer and MAC layer
devices, and has the following key characteristics:
• Supports 10Mbps and 100Mbps data rates.
• Uses a 25MHz reference clock, sourced by the PHY.
• Provides independent 4-bit wide (nibble) transmit and
receive data paths.
• Contains two distinct groups of signals: one for
transmission and the other for reception.
The ICS1894-33 is configured for MII mode upon power-up
or hardware reset with the following:
• A 25MHz crystal connected to REFIN, REFOUT (pins 30,
29), or an external 25MHz clock source (oscillator)
connected to REFIN
Reduced MII (RMII) Data Interface
The Reduced Media Independent Interface (RMII) specifies
a low pin count Media Independent Interface (MII). It
provides a common interface between physical layer and
MAC layer devices, and has the following key
characteristics:
• Supports 10Mbps and 100Mbps data rates.
• Uses a single 50MHz reference clock provided by the
MAC or the system board.
• Provides independent 2-bit wide (di-bit) transmit and
receive data paths.
• Contains two distinct groups of signals: one for
transmission and the other for reception.
In RMII mode, a 50 MHz reference clock is connected to
REFIN(pin 30).
Preamble Start of
Frame
Read/Write
OP Code
PHY Address
Bits [4:0]
REG Address
Bits [4:0]
TA Data Bits
[15:0]
Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
ICS1894-33
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 9
ICS1894-33 REV A 021612
RMII Signal Definition
The following table describes the RMII signals. Refer to RMII Specification for detailed information.
Reference Clock (REFIN)
REFIN is sourced by the MAC or system board. It is a
continuous 50MHz clock that provides the timing reference
for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER.
Transmit Enable (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on
TXD[1:0] for transmission. It is asserted synchronously with
the first nibble of the preamble and remains asserted while
all di-bits to be transmitted are presented on the RMII, and
is negated prior to the first REFIN following the final di-bit of
a frame. TX_EN transitions synchronously with respect to
REFIN.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REFIN.
When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is ”00” to indicate idle
when TX_EN is de-asserted. Values other than “00” on
TXD[1:0] while TX_EN is de-asserted are ignored by the
PHY.
Carrier Sense/Data Valid (CRS_DV[RXDV])
CRS_DV, identified as RXDV (pin 18), shall be asserted by
the PHY when the receive medium is non-idle. The specifics
of the definition of idle for 10BASE-T and 100BASE-X are
contained in IEEE 802.3 [1] and IEEE 802.3u [2]. CRS_DV
is asserted asynchronously on detection of carrier due to
the criteria relevant to the operating mode. That is, in
10BASE-T mode, when squelch is passed or in 100BASE-X
mode when 2 non-contiguous zeroes in 10 bits are detected
carrier is said to be detected.
Loss of carrier shall result in the deassertion of CRS_DV
synchronous to the cycle of REFIN which presents the first
di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted
only on nibble boundaries). If the PHY has additional bits to
be presented on RXD[1:0] following the initial deassertion of
CRS_DV, then the PHY shall assert CRS_DV on cycles of
REFIN which present the second di-bit of each nibble and
deassert CRS_DV on cycles of REFIN which present the
first di-bit of a nibble. The result is: Starting on nibble
boundaries CRS_DV toggles at 25 MHz in 100Mb/s mode
and 2.5 MHz in 10Mb/s mode when the Carrier event ends
before the RX_DV signal internal to the PHY is deasserted
(i.e. the FIFO still has bits to transfer when the carrier event
ends.) Therefore, the MAC can accurately recover RX_DV
and the Carrier event end time. During a false carrier event,
CRS_DV shall remain asserted for the duration of carrier
activity.
The data on RXD[1:0] is considered valid once CRS_DV is
asserted. However, since the assertion of CRS_DV is
asynchronous relative to REFIN, the data on RXD[1:0] shall
be "00" until proper receive signal decoding takes place (see
definition of RXD[1:0] behavior).
*Note: CRS_DV is asserted asynchronously in order to
minimize latency of control signals through the PHY.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REFIN. For each
clock period in which CRS_DV is asserted, RXD[1:0]
transfers two bits of recovered data from the PHY. RXD[1:0]
is "00" to indicate idle when CRS_DV is de-asserted. Values
other than “00” on RXD[1:0] while CRS_DV is de-asserted
are ignored by the MAC.
RMII Signal Name Direction
(with respect to PHY,
ICS1894-33 signal)
Direction
(with respect to MAC)
Description
REFIN Input Input or Output Synchronous 50 MHz clock reference for
receive, transmit and control interface
TXEN Input Output Transmit Enable
TXD[1:0] Input Output Transmit Data [1:0]
RXD[1:0 Output Input Receive Data [1:0]
RXER Output Input, or (not required) Receive Error
CRS_DV[RXDV] Output Input Carrier Sense/Data Valid
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

1894K-33LFT

Mfr. #:
Buy 1894K-33LFT
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
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