ICS1894-33
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 22
ICS1894-33 REV A 021612
Register 19 - Extended Control Register
19.15 Node Mode Node mode Repeater mode (mode not
supported)
RW L
19.14 Hardware/Software
Mode Speed Select
Use bit00.13 to select
speed
Use real time input pin 22
only to select speed
RW L
19.13 Remote Fault No faults detected Remote fault detected RO 0
19.12 Register Bank select [01]=Bank1, access register0x00~0x13 and
ICS1893CF registers 0x14~0x1F
[00]=Bank0, access register0x00~0x13, new defined
registers 0x14~0x25
[1x]=Bank0, same as [00]
RW 0
19.11 RW 0 2
19.10 ICS reserved Reserved Reserved RO 0
19.9 AMDIX_EN See Table on page 11 See Table on page 11 RW 1
19.8 MDI_MODE See Table on page 11 See Table on page 11 RW 0
19.7 Twisted Pair Tri-State
Enable, TPTRI
Twisted Pair Signals are
not Tri-Stated or No
effect
Twisted Pair Signals are
Tri-Stated
RW 0 0
19.6 ICS reserved Reserved Reserved RW 0
19.5 ICS reserved Reserved Reserved RW 0
19.4 ICS reserved Reserved Reserved RW 0
19.3 ICS reserved Reserved Reserved RW 0 1
19.2 ICS reserved Reserved Reserved RW 0
19.1 ICS reserved Reserved Reserved RW 0
19.0 Automatic 100Base-TX
Power Down
Do not automatically
power down
Power down automatically RW 1
Register
20 - Extended Control Register
20.15 Str_enhance Normal digital output
strength
Enhance digital output
strength in 1.8V condition
RW 0
3
20.14 ICS reserved Reserved Reserved RW 0
20.13 ICS reserved Reserved Reserved RW 1
20.12 1
Bit Definition When Bit = 0 When Bit = 1 Access
2
SF
2
Default
3
Hex
ICS1894-33
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 23
ICS1894-33 REV A 021612
20.11 ICS reserved Reserved Reserved RW 1
F
20.10 1
20.9 1
20.8
ICS reserved
Reserved Reserved RW 1
20.7 1
E
20.6 1
20.5 LED1 Mode 000 = Link Integrity
001 = activity/no activity
010 = Transmit Data
011 = Receive Data
100 = Not supported
101 = 100/10 mode (Default LED1)
110 = Full Duplex
111 = OFF
RW 1
20.4 0
20.3 1
9
20.2 LED0 Mode 000 = Link Integrity
001 = activity/no activity (Default LED0)
010 = Transmit Data
011 = Receive Data
100 = Not supported
101 = 100/10 mode
110 = Full Duplex
111 = LINK_STAT
RW 0
20.1 0
20.0 1
Register
21 - Extended Control Register
21.15:0 RXER_CNT Receive error count for RMII mode RW
0
Register 22 - Extended Control Register
22.15 Interrupt output enable Disable interrupt output Enable interrupt output RW 0
0
22.14 Interrupt flag read clear
enable
Interrupt flag clear by
read disable
Interrupt flag clear by read
enable
RW 0
22.13 Interrupt polarity Output low when
interrupt occur
Output high when
interrupt occur
RW 0
22.12 Interrupt flag auto clear
enable
Interrupt flag unchanged
when interrupt condition
removed
Interrupt flag cleared
when interrupt condition
removed
RW 0
22.11 Interrupt flag re-setup
enable
Interrupt flag always
cleared when write 1 to
flag bit
Interrupt flag remains
unchanged when
interrupt condition exists
when a 1 is written to flag
bit.
RW 0
0
22.10 Interrupt Enable Disable Deep power
down wake up Interrupt
Enable Deep power down
wake up Interrupt
RW 0
22.9 Interrupt Enable Disable Deep power
down Interrupt
Enable Deep power down
Interrupt
RW 0
22.8 Interrupt Enable Disable Auto-Negotiation
Complete Interrupt
Enable Auto-Negotiation
Complete Interrupt
RW 0
Bit Definition When Bit = 0 When Bit = 1 Access
2
SF
2
Default
3
Hex
ICS1894-33
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 24
ICS1894-33 REV A 021612
22.7 Interrupt Enable Disable Jabber Interrupt Enable Jabber Interrupt RW 0
0
22.6 Interrupt Enable Disable Receive Error
Interrupt
Enable Receive Error
Interrupt
RW 0
22.5 Interrupt Enable Disable Page Received
Interrupt
Enable Page Received
Interrupt
RW 0
22.4 Interrupt Enable Disable Parallel Detect
Fault Interrupt
Enable Parallel Detect
Fault Interrupt
RW 0
22.3 Interrupt Enable Disable Link Partner
Acknowledge Interrupt
Enable Link Partner
Acknowledge Interrupt
RW 0
0
22.2 Interrupt Enable Disable Link Down
Interrupt
Enable Link Down
Interrupt
RW 0
22.1 Interrupt Disable Remote Fault
Interrupt
Enable Remote Fault
Interrupt
RW 0
22.0 Enable Disable Link Up Interrupt Enable Link Up Interrupt RW 0
Register
23 - Extended Control Register
23.15:11 Reserved Reserved RO 0
0
23.10 Deep power down wake
up Interrupt
Deep power down wake
up did not occur
Deep power down wake
up occurred
RO/SC 0
0
23.9 Deep power down
Interrupt
Deep power down did
not occur
Deep power down
occurred
RO/SC 0
23.8 Auto-Negotiation
Interrupt
Auto-Negotiation
Complete did not occur
Auto-Negotiation
Complete occurred
RO/SC 0
23.7 Jabber Interrupt Jabber did not occur Jabber occurred RO/SC 0
0
23.6 Receive Error Interrupt Receive Error did not
occur
Receive Error occurred RO/SC 0
23.5 Page Receive Interrupt Page Receive did not
occur
Page Receive occurred RO/SC 0
23.4 Parallel Detect Fault
Interrupt
Parallel Detect Fault did
not occur
Parallel Detect Fault
occurred
RO/SC 0
23.3 Link Partner
Acknowledge Interrupt
Link Partner
Acknowledge did not
occur
Link Partner Acknowledge
occurred
RO/SC 0
0
23.2 Link Down Interrupt Link Down did not occur Link Down occurred RO/SC 0
23.1 Remote Fault Interrupt Remote Fault did not
occur
Remote Fault occurred RO/SC 0
23.0 Link Up Interrupt Link Up did not occur Link Up occurred RO/SC 0
Register 24 - Extended Control Register
24.15:12 FIFO Half RMII FIFO half full bits ((n+3)*2 bit), RMII RW 2 2
24.11:9 Reserved Reserved RW 0 0
24.8 Deep Power down
enable
Deep power down(DPD)
disable
Deep power down(DPD)
enable
RW 0
Bit Definition When Bit = 0 When Bit = 1 Access
2
SF
2
Default
3
Hex

1894K-33LFT

Mfr. #:
Manufacturer:
IDT
Description:
Ethernet ICs 3.3V 10/100 PHY RMII
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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