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EPCQ64ASI16N

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
1.4. Pin Information
1.4.1. Pin-Out Diagram for EPCQ4A, EPCQ16A and EPCQ32A Devices
Figure 2. AS x1 and AS x4 Pin-Out Diagrams for EPCQ4A, EPCQ16A, and EPCQ32A
Devices
Note: EPCQ4A supports AS x1 only.
nCS
DATA1
V
CC
GND
V
CC
V
CC
DCLK
DATA0
1
2
3
4
8
7
6
5
nCS
DATA1
DATA2
GND
V
CC
DATA3
DCLK
DATA0
1
2
3
4
8
7
6
5
AS x1 AS x4
1.4.2. Pin-Out Diagram for EPCQ64A and EPCQ128A Devices
Figure 3. AS x1 and AS x4 Pin-Out Diagrams for EPCQ64A and EPCQ128A Devices
V
CC
V
CC
nRESET
N.C
N.C
N.C
nCS
DATA1
DCLK
DATA0
N.C.
N.C
N.C
N.C
GND
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DATA3
V
CC
nRESET
N.C
N.C
N.C
nCS
DATA1
DCLK
DATA0
N.C.
N.C
N.C
N.C
GND
DATA2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AS x1 AS x4
Notes:
There is an internal pull-up resistor for the dedicated nRESET pin. If the reset function is not needed,
connect this pin to Vcc or leave it unconnected.
N.C pins must be left unconnected.
1. EPCQ-A Serial Configuration Device Datasheet
CF52014 | 2018.04.11
EPCQ-A Serial Configuration Device Datasheet
7
1.4.3. EPCQ-A Device Pin Description
Table 8. EPCQ-A Device Pin Description
Pin Name AS x1 Pin-Out
Diagram
AS x4 Pin-Out
Diagram
Pin Type Description
Pin
Number
in 8-Pin
SOIC
Package
Pin
Number
in 16-Pin
SOIC
Package
Pin
Number
in 8-Pin
SOIC
Package
Pin
Number
in 16-Pin
SOIC
Package
DATA0
5 15 5 15 I/O For AS x1 mode, use this pin as an input signal
pin to write or program the EPCQ-A device.
During write or program operations, data are
latched at rising edges of the DCLK signal. This
pin is equivalent to the ASDI pin in EPCS devices.
For AS x4 mode, use this pin as an I/O signal pin.
During write or program operations, this pin acts
as an input pin that serially transfers data into
the EPCQ-A device. The data are latched at rising
edges of the DCLK signal. During read or
configuration operations, this pin acts as an
output signal pin that serially transfers data out
of the EPCQ-A device to the FPGA. The data is
shifted out at falling edges of the DCLK signal.
During the quad input fast write bytes operation,
this pin acts as an input pin that serially transfers
data into the EPCQ-A device. The data is latched
at rising edges of the DCLK signal. During
extended dual input fast read or extended quad
input fast read operations, this pin acts as an
output signal pin that serially transfers data out
of the EPCQ-A device to the FPGA. The data is
shifted out at falling edges of the DCLK signal.
DATA1
2 8 2 8 I/O For AS x1 and x4 modes, use this pin as an
output signal pin that serially transfers data out
of the EPCQ-A device to the FPGA during read or
configuration operations. The transition of the
signal is at falling edges of the DCLK signal. This
pin is equivalent to the DATA pin in EPCS devices.
During the quad input fast write bytes operation,
this pin acts as an input signal pin that serially
transfers data into the EPCQ-A device. The data is
latched at rising edges of the DCLK signal.
During extended quad input fast read operations,
this pin acts as an output signal pin that serially
transfer data out of the EPCQ-A device to the
FPGA. The data is shifted out at falling edges of
the DCLK signal. During read, configuration, or
program operations, you can enable the EPCQ-A
device by pulling the nCS signal low.
DATA2
— — 3 9 I/O For AS x1 mode, this pin must connect to V
CC
.
For AS x4 mode, use this pin as an output signal
that serially transfers data out of the EPCQ-A
device to the FPGA during read or configuration
operations. The transition of the signal is at
falling edges of the DCLK signal.
During the extended quad input fast read
operation, this pin acts as an output signal pin
that serially transfers data out of the EPCQ-A
device to the FPGA. The data is shifted out at
falling edges of the DCLK signal.
continued...
1. EPCQ-A Serial Configuration Device Datasheet
CF52014 | 2018.04.11
EPCQ-A Serial Configuration Device Datasheet
8
Pin Name AS x1 Pin-Out
Diagram
AS x4 Pin-Out
Diagram
Pin Type Description
Pin
Number
in 8-Pin
SOIC
Package
Pin
Number
in 16-Pin
SOIC
Package
Pin
Number
in 8-Pin
SOIC
Package
Pin
Number
in 16-Pin
SOIC
Package
DATA3
— — 7 1 I/O For AS x1 mode, this pin must connect to V
CC
.
For AS x4 mode, use this pin as an output signal
that serially transfers data out of the EPCQ-A
device to the FPGA during read or configuration
operations. The transition of the signal is at
falling edges of the DCLK signal.
During the extended quad input fast read
operation, this pin acts as an output signal pin
that serially transfers data out of the EPCQ-A
device to the FPGA. The data is shifted out at
falling edges of the DCLK signal.
nCS
1 7 1 7 Input
The active low nCS input signal toggles at the
beginning and end of a valid operation. When this
signal is high, the device is deselected and the
DATA[3:0] pins are tri-stated. When this signal
is low, the device is enabled and is in active
mode. After power up, the EPCQ-A device
requires a falling edge on the nCS signal before
you begin any operation.
DCLK
6 16 6 16 Input
The FPGA provides the DCLK signal. This signal
provides the timing for the serial interface. The
data presented on the DATA[3:0] pins are
latched to the EPCQ-A device at rising edges of
the DCLK signal. The data on the DATA[3:0]
pins change after the falling edge of the DCLK
signal and are latched in to the FPGA on the next
falling edge of the DCLK signal.
nRESET
— 3 — 3 Input Dedicated hardware reset pin. When it’s driven
low for a minimum period of ~1μS, the EPCQ-A
device will terminate any external or internal
operations and return to its power-on state.
There is an internal pull-up resistor for the
dedicated nRESET pin on the SOIC-16 package. If
the reset function is not needed, you can connect
it to V
CC
or leave it unconnected.
V
CC
8 2 8 2 Power Connect the power pins to a 3.3-V power supply.
GND 4 10 4 10 Ground Ground pin.
1.5. Device Package and Ordering Code
1.5.1. Package
The EPCQ4A, EPCQ16A, and EPCQ32A devices are available in 8-pin SOIC packages.
The EPCQ64A and EPCQ128A devices are available in 16-pin SOIC packages.
1. EPCQ-A Serial Configuration Device Datasheet
CF52014 | 2018.04.11
EPCQ-A Serial Configuration Device Datasheet
9
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

EPCQ64ASI16N

Mfr. #:
Buy EPCQ64ASI16N
Manufacturer:
Intel / Altera
Description:
FPGA - Configuration Memory
Lifecycle:
New from this manufacturer.
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