LTC1966
19
1966fb
applicaTions inForMaTion
Step Responses with a Post Filter
B
oth of the post filters, shown in Figures 13 and 14,
are optimized for additional filtering with clean step
responses. The 85kΩ output impedance of the LTC1966
working into a 1µF capacitor forms a 1st order LPF with
a –3dB frequency of ~1.8Hz. The two filters have 1µF at
the LTC1966 output for easy comparison with a 1µF only
case, and both have the same relative (Bessel-like) shape.
However, because of the topological differences of pole
placements between the various components within the
two filters, the net effective bandwidth for Figure 13 is
slightly higher (≈1.2 • 1.8 ≈ 2.1Hz) than with 1µF alone,
while the bandwidth for Figure 14 is somewhat lower
(≈0.7 1.8 1.3Hz) than with 1µF alone. To adjust the
bandwidth of either of them, simply scale all the capacitors
by a common multiple, and leave the resistors unchanged.
The step responses of the LTC1966 with 1µF only and with
the two post filters are shown in Figure 15. This is the ris-
ing edge RMS output response to a 10Hz input starting
at t = 0. Although the falling edge response is the worst
case for settling, the rising edge illustrates the ripple that
these post filters are designed to address, so the rising
edge makes for a better intuitive comparison.
The initial rise of the LTC1966 will have enhanced slew rates
with DC and very low frequency inputs due to saturation
effects in the ∆S modulator. This is seen in Figure 15 in
two ways. First, the 1µF only output is seen to rise very
quickly in the first 40ms. The second way this effect shows
up is that the post filter outputs have a modest overshoot,
on the order of 3mV to 4mV, or 3% to 4%. This is only
an issue with input frequency bursts at 50Hz or less, and
even with the overshoot, the settling to a given level of
accuracy improves due to the initial speedup.
As predicted by Figure 6, the DC error with 1µF is well
under 1mV and is not noticeable at this scale. However, as
predicted by Figure 8, the peak error with the ripple from a
10Hz input is much larger, in this case about 5mV. As can
be clearly seen, the post filters reduce this ripple. Even
the wider bandwidth of Figure 13’s filter is seen to cut the
ripple down substantially (to <1mV) while the settling to
1% happens faster. With the narrower bandwidth of Figure
14’s filter, the step response is somewhat slower, but the
double frequency output ripple is just 180µV.
Figure 16 shows the step response of the same three cases
with a burst of 60Hz rather than 10Hz. With 60Hz, the ini-
tial portion of the step response is free of the boost seen
in Figure 15 and the two post filter responses have less
than 1% overshoot. The 1µF only case still has noticeable
120Hz ripple, but both filters have removed all detectable
ripple on this scale. This is to be expected; the first order
filter will reduce the ripple about 6:1 for a 6:1 change in
frequency, while the third order filters will reduce the
ripple about 6
3
:1 or 216:1 for a 6:1 change in frequency.
Again, the two filter topologies have the same relative
shape, so the step response and ripple filtering trade-offs of
the two are the same, with the same performance of each
possible with the other by scaling it accordingly. Figures
17 and 18 show the peak error vs. frequency for a selec-
tion of capacitors for the two different filter topologies.
To keep the clean step response, scale all three capacitors
Figure 16. Step Responses with 60Hz Burst
Figure 15. Step Responses with 10Hz Burst
INPUT
BURST
200mV/
DIV
20mV/
DIV
0
0
1µF ONLY
FIGURE 13
FIGURE 14
STEP
RESPONSE
100ms/DIV
1966 F15
INPUT
BURST
200mV/
DIV
20mV/
DIV
0
0
1µF ONLY
FIGURE 13
FIGURE 14
STEP
RESPONSE
100ms/DIV
1966 F16
LTC1966
20
1966fb
applicaTions inForMaTion
within the filter. Scaling the buffered topology of Figure 13
is simple because the capacitors are in a 10:1:10 ratio.
Scaling the DC accurate topology of Figure 14 can be done
with standard value capacitors; one decade of scaling is
shown in Table 2.
Table 2. One Decade of Capacitor Scaling for Figure 14 with EIA
Standard Values
C
AVE
C
1
= C
2
=
F 0.22µF
1.5µF 0.33µF
2.2µF 0.47µF
3.3µF 0.68µF
4.7µF F
6.8µF 1.5µF
Figures 19 and 20 show the settling time versus settling
accuracy for the buffered and DC accurate post filters,
respectively. The different curves represent different scal-
ings of the filters, as indicated by the C
AVE
value. These are
comparable to the curves in Figure 12 (single capacitor
case), with somewhat less settling time for the buffered
post filter, and somewhat more settling time for the DC
accurate post filter. These differences are due to the change
in overall bandwidth as mentioned earlier.
The other difference is the settling behavior of the filters
below the 1% level. Unlike the case of a 1st order filter,
any 3rd order filter can have overshoot and ringing. The
filter designs presented here have minimal overshoot
and ringing, but are somewhat sensitive to component
mismatches. Even the ±12% tolerance of the LTC1966
output impedance can be enough to cause some ringing.
The dashed lines indicate what can happen when ±5%
capacitors and ±1% resistors are used.
Figure 18. Peak Error vs Input Frequency with DC Accurate Post Filter
Figure 17. Peak Error vs Input Frequency with Buffered Post Filter
INPUT FREQUENCY (Hz)
1
2.0
PEAK ERROR (%)
–1.6
–1.2
0.8
0.4
10 100
1966 F17
0
–1.8
–1.4
–1.0
0.6
0.2
C = 10µF
C = 4.7µF C = 2.2µF C = 1.0µF C = 0.47µF C = 0.22µF
C = 0.1µF
INPUT FREQUENCY (Hz)
1
2.0
PEAK ERROR (%)
–1.6
–1.2
0.8
0.4
10 100
1966 F18
0
–1.8
–1.4
–1.0
0.6
0.2
C = 10µF
C = 4.7µF
C = 2.2µF C = 1.0µF C = 0.47µF C = 0.22µF C = 0.1µF
LTC1966
21
1966fb
applicaTions inForMaTion
Although the settling times for the post filtered configu-
rations shown on Figures 19 and 20 are not that much
different from those with a single capacitor, the point of
using a post filter is that the settling times are far better
for a given level peak error. The filters dramatically reduce
the low frequency averaging ripple with far less impact
on settling time.
Crest Factor and AC + DC Waveforms
In the preceding discussion, the waveform was assumed
to be AC-coupled, with a modest crest factor. Both as-
sumptions ease the requirements for the averaging
capacitor. With an AC-coupled sine wave, the calculation
engine squares the input, so the averaging filter that
follows is required to filter twice the input frequency,
making its job easier. But with a sinewave that includes
DC offset, the square of the input has frequency content
at the input frequency and the filter must average out
that lower frequency. So with AC + DC waveforms, the
required value for C
AVE
should be based on half of the
lowest input frequency, using the same design curves
presented in Figures 6, 8, 17 and 18.
Crest factor, which is the peak to RMS ratio of a dynamic
signal, also effects the required C
AVE
value. With a higher
crest factor, more of the energy in the signal is concen-
trated into a smaller portion of the waveform, and the
averaging has to ride out the long lull in signal activity.
For busy waveforms, such as a sum of sine waves, ECG
traces or SCR chopped sine waves, the required value for
C
AVE
should be based on the lowest fundamental input
frequency divided as such:
f
f
CF
DESIGN
INPUT MIN
=
•–
Figure 20. Settling Time with DC Accurate Post Filter
Figure 19. Settling Time with Buffered Post Filter
SETTLING TIME (SEC)
0.01
0.1
SETTLING ACCURACY (%)
1
10
10.1 10 100
1066 F14
C = 100µFC = 47µFC = 22µFC = 10µFC = 4.7µFC = 2.2µFC = 1.0µFC = 0.47µFC = 0.22µFC = 0.1µF
SETTLING TIME (SEC)
0.01
0.1
SETTLING ACCURACY (%)
1
10
10.1 10 100
1066 F20
C = 100µFC = 47µFC = 22µFC = 10µFC = 4.7µFC = 2.2µFC = 1.0µFC = 0.47µFC = 0.22µFC = 0.1µF

LTC1966MPMS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC Prec uP, DS RMS-to-DC Conv
Lifecycle:
New from this manufacturer.
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