LTC1966
22
1966fb
applicaTions inForMaTion
using the same design curves presented in Figures 6, 8,
17 and 18. For the worst-case of square top pulse trains,
that are always either zero volts or the peak voltage, base
the selection on the lowest fundamental input frequency
divided by twice as much:
f
f
CF
DESIGN
INPUT MIN
=
•–
The effects of crest factor and DC offsets are cumulative.
So for example, a 10% duty cycle pulse train from 0V
PEAK
to 1V
PEAK
(CF = √10 = 3.16) repeating at 16.67ms (60Hz)
input is effectively only 30Hz due to the DC asymmetry
and is effectively only:
z
DESIGN
30
6316 2
378
•.–
.
for the purposes of Figures 6, 8, 17 and 18.
Obviously, the effect of crest factor is somewhat simplified
above given the factor of 2 difference based on a subjec-
tive description of the waveform type. The results will vary
somewhat based on actual crest factor and waveform
dynamics and the type of filtering used. The above method
is conservative for some cases and about right for others.
The LTC1966 works well with signals whose crest factor is
4 or less. At higher crest factors, the internal ∆∑ modulator
will saturate, and results will vary depending on the exact
frequency, shape and (to a lesser extent) amplitude of the
input waveform. The output voltage could be higher or
lower than the actual RMS of the input signal.
The ∆∑ modulator may also saturate when signals with crest
factors less than 4 are used with insufficient averaging.
This will only occur when the output droops to less than
1/4 of the input voltage peak. For instance, a DC-coupled
pulse train with a crest factor of 4 has a duty cycle of
6.25% and a 1V
PEAK
input is 250mV
RMS
. If this input is
50Hz, repeating every 20ms, and C
AVE
= 1µF, the output
will droop during the inactive 93.75% of the waveform.
This droop is calculated as:
V
V
e
MIN
RMS
INACTIVE TIME
=
−
2
1–
2 • Z• C
OUT AVE
For the LTC1966, whose output impedance (Z
OUT
) is 85kΩ,
this droop works out to –5.22%, so the output would be
reduced to 237mV at the end of the inactive portion of the
input. When the input signal again climbs to 1V
PEAK
, the
peak/output ratio is 4.22.
With C
AVE
= 10µF, the droop is only –0.548% to 248.6mV
and the peak/output ratio is just 4.022, which the LTC1966
has enough margin to handle without error.
For crest factors less than 3.5, the selection of C
AVE
as
previously described should be sufficient to avoid this
droop and modulator saturation effect. But with crest
factors above 3.5, the droop should also be checked for
each design.
Error Analyses
Once the RMS-to-DC conversion circuit is working, it is
time to take a step back and do an analysis of the accuracy
of that conversion. The LTC1966 specifications include
three basic static error terms, V
OOS
, V
IOS
and GAIN. The
output offset is an error that simply adds to (or subtracts
from) the voltage at the output. The conversion gain of
the LTC1966 is nominally 1.000 V
DCOUT
/V
RMSIN
and the
gain error reflects the extent to which this conversion gain
is not perfectly unity. Both of these affect the results in a
fairly obvious way.
Input offset on the other hand, despite its conceptual
simplicity, effects the output in a nonobvious way. As
its name implies, it is a constant error voltage that adds
directly with the input. And it is the sum of the input and
V
IOS
that is RMS converted.
This means that the effect of V
IOS
is warped by the
nonlinear RMS conversion. With 0.2mV (typ) V
IOS
, and
a 200mV
RMS
AC input, the RMS calculation will add the
DC and AC terms in an RMS fashion and the effect is
negligible:
V
OUT
= √(200mV AC)
2
+ (0.2mV DC)
2
= 200.0001mV
= 200mV + 1/2ppm
