LTC1966
31
1966fb
The calculations of the error terms for a 200mV full-scale
case are:
Gain =
Reading at 200mV Reading at 20mV
180mV
Output Offset =
Reading at 20mV
Gain
–20mV
DC, 2 Point
DC based calibration is preferable in many cases because a
DC voltage of known, good accuracy is easier to generate
than such an AC calibration voltage. The only down side
is that the LTC1966 input offset voltage plays a role. It is
therefore suggested that a DC based calibration scheme
check at least two points: ±full-scale. Applying the –full-
scale input can be done by physically inverting the voltage
or by applying the same +full-scale input to the opposite
LTC1966 input.
For an otherwise AC-coupled application, only the gain
term may be worth correcting for, but for DC-coupled ap-
plications, the input offset voltage can also be calculated
and corrected for.
The calculations of the error terms for a 200mV full-scale
case are:
Gain =
Reading at 200mV +Reading at 200mV
400mV
Input Offset =
Reading at 200mV Reading at 200mV
2•Gain
applicaTions inForMaTion
Note: Calculation of and correction for input offset voltage
are the only way in which the two LTC1966 inputs (IN1,
IN2) are distinguishable from each other. The calculation
above assumes the standard definition of offset; that a
positive offset is the case of a positive voltage error inside
the device that must be corrected by applying a like nega-
tive voltage outside. The offset is referred to whichever
pin is driven positive for the +full-scale reading.
DC, 3 Point
One more point is needed with a DC calibration scheme
to determine output offset voltage: +10% of full scale.
The calculation of the input offset is the same as for the
2-point calibration above, while the gain and output offset
are calculated for a 200mV full-scale case as:
Gain =
Reading at 200mV Reading at 20mV
180mV
Output Offset =
Reading at 200mV +Reading at 200mV 400mV Gain
2
LTC1966
32
1966fb
TROUBLESHOOTING GUIDE
Top Ten LTC1966 Application Mistakes
1. Circuit won’t work–Dead On Arrival–no power drawn.
Probably forgot to enable the LTC1966 by pulling
Pin8 low.
Solution: Tie Pin 8 to Pin 1.
2. Circuit won’t work, but draws power. Zero or
very little output, single-ended input application.
Probably didn’t connect both input pins.
Solution: Tie both inputs to something. See Input
Connections in the Design Cookbook.
applicaTions inForMaTion
4. Gain is low by a few percent, along with other screwy
results.
Probably tried to use output in a floating, differential
manner.
Solution: Tie Pin 6 to a low impedance. See Output
Connections in the Design Cookbook.
TYPE 7136
ADC
LTC1966
HI
31
30
5
6
LO
V
OUT
OUT RTN
1966 TS04
GROUND PIN 6
LTC1966
CONNECT PIN 3
IN1
2
3
NC
IN2
1966 TS02
3. Screwy results, particularly with respect to linearity
or high crest factors; differential input application.
Probably AC-coupled both input pins.
Solution: Make at least one input DC-coupled. See
Input Connections in the Design Cookbook.
LTC1966
IN1
2
3
IN2
1966 TS03
DC CONNECT ONE INPUT
LTC1966
DC CONNECT ONE INPUT
IN1
2
3
IN2
5. Offsets perceived to be out of specification because 0V
in ≠ 0V out.
The offsets are not specified at 0V in. No RMS-to-DC
converter works well at 0 due to a divide-by-zero
calculation.
Solution: Measure V
IOS
/V
OOS
by extrapolating
readings > ±5mV
DC
.
6. Linearity perceived to be out of specification particularly
with small input signals.
This could again be due to using 0V in as one of the
measurement points.
Solution: Check Linearity from 5mV
RMS
to 500mV
RMS
.
The input offset voltage can cause small AC
linearity errors at low input amplitudes as well. See
Error Analyses section.
Possible Solution: Include a trim for input offset.
LTC1966
33
1966fb
applicaTions inForMaTion
7. Output is noisy with >10kHz inputs.
This is a fundamental characteristic of this topol-
ogy. The LTC1966 is designed to work very well
with inputs of 1kHz or less. It works okay as high
as 1MHz, but it is limited by aliased ∆S noise.
Solution: Bandwidth limit the input or digitally filter
the resulting output.
8. Large errors occur at crest factors approaching, but
less than 4.
Insufficient averaging.
Solution: Increase C
AVE
. See Crest Factor and AC + DC
Waveforms section for discussion of output droop.
9. Screwy results, errors > spec limits, typically 1% to 5%.
High impedance (85kΩ) and high accuracy (0.1%)
require clean boards! Flux residue, finger grime, etc.
all wreak havoc at this level.
Solution: Wash the board.
Helpful Hint: Sensitivity to leakages can be reduced
significantly through the use of guard traces.
LTC1966
KEEP BOARD CLEAN
10. Gain is low by 1% or more, no other problems.
Probably due to circuit loading. With a DMM or
a 10× scope probe, Z
IN
= 10MΩ. The LTC1966
output is 85kΩ, resulting in –0.85% gain error.
Output impedance is higher with the DC accurate
post filter.
Solution: Remove the shunt loading or buffer the
output.
– Loading can also be caused by cheap averaging
capacitors.
Solution: Use a high quality metal film capacitor
for C
AVE
.
200mV
RMS
IN
–0.85%
DMM
DCV
LTC1966
10M
5
85k
6
V
OUT
OUT RTN
1966 TS10
LOADING DRAGS DOWN GAIN
mV

LTC1966MPMS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC Prec uP, DS RMS-to-DC Conv
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