LTC1966
25
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applicaTions inForMaTion
The two 10MΩ resistors not connected to the supply can
be any value as long as they match and the feed voltage
is changed for 30nA injection. The op amp gain is only
1.00845, so the output is dominated by the LTC1966 RMS
results, which keeps errors low. With the values shown,
the resistors can be ±2% and only introduce ±170ppm of
gain error. The 84.5k resistor is the closest match in the
1% EIA values but if the 2% EIA value of 82k were used
instead, the gain would only be reduced by 248ppm.
This low error sensitivity is important because the LTC1966
output impedance is 85kΩ ±11.8%, which can create a
gain error of ±0.1%; enough to degrade the overall gain
accuracy somewhat. This gain variation term is increased
with lower value feed resistors, and decreased with higher
value feed resistors.
A bigger error caused by the variation of the LTC1966
output impedance is imperfect cancelation of the output
offset introduced by the injected current. The offset correc-
tion provided by the LT1494 will be based on a consistent
84.5kΩ times the injected current, while the LTC1966 output
impedance will vary enough that the output offset will have
a ±300µV range about the nominal 2.5mV. If this level of
output offset is not acceptable, either system calibration
or a potentiometer in the LT1494 feedback may be needed.
If the two 10MΩ feed resistors to the LT1494 have signifi-
cant mismatch, cancellation of the 2.5mV offset would be
further impacted, so it is probably worth paying an extra
penny or so for 1% resistors or even the better temperature
stability of thin film devices. The 300mV feed voltage is
not particularly critical because it is nominally cancelled,
but the offset errors due to these resistance mismatches
is scaled by that voltage.
Note that the input bias current of the op amp used in
Figure 23 is also nominally cancelled, but it will add or
subtract to the total current injected into the LTC1966
output. With the 1nA I
BIAS
of the LT1494 this is negligible.
While it is possible to eliminate the feed resistors by using
an op amp with a PNP input stage whose I
BIAS
is 30nA
or more, I
BIAS
is usually only specified for maximum and
this circuit needs a minimum of 30nA, therefore such an
approach may not always work.
Because the circuit of Figure 23 subtracts the offset cre-
ated by the injected current, the LT1494 output with zero
LTC1966 input will rest at +2.5mV, nominal before offsets,
rather then the 5mV seen in Figure 22.
Output Errors Versus Frequency
As mentioned in the Design Cookbook, the LTC1966 per-
forms very well with low frequency and very low frequency
inputs, provided a large enough averaging capacitor is used.
However, the LTC1966 will have additional dynamic errors as
the input frequency is increased. The LTC1966 is designed
for high accuracy RMS-to-DC conversion of signals into
the audible range. The input sampling amplifiers have a
3dB frequency of 800kHz or so. However, the switched
capacitor circuitry samples the inputs at a modest 100kHz
nominal. The response versus frequency is depicted in the
Typical Performance Characteristics titled Input Signal
Bandwidth. Although there is a pattern to the response
versus frequency that repeats every sample frequency, the
errors are not overwhelming. This is because LTC1966 RMS
calculation is inherently wideband, operating properly with
minimal oversampling, or even undersampling, using sev-
eral proprietary techniques to exploit the fact that the RMS
value of an aliased signal is the same as the RMS value of
the original signal. However, a fundamental feature of the
S modulator is that sample estimation noise is shaped
such that minimal noise occurs with input frequencies
much less than the sampling frequency, but such noise
peaks when input frequency reaches half the sampling
frequency. Fortunately the LTC1966 output averaging filter
greatly reduces this error, but the RMS-to-DC topology
frequency shifts the noise to low (baseband) frequencies.
So with input frequencies above 5kHz to 10kHz, the output
will slowly wander around ±a few percent.
LTC1966
26
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applicaTions inForMaTion
Input Impedance
The LTC1966 true RMS-to-DC converter utilizes a 2.5pF
capacitor to sample the input at a nominal 100kHz sample
frequency. This accounts for the 8MΩ input impedance.
See Figure 24 for the equivalent analog input circuit. Note
however, that the 8MΩ input impedance does not directly
affect the input sampling accuracy. For instance, if a 100k
source resistance is used to drive the LTC1966, the sampling
action of the input stage will drag down the voltage seen
at the input pins with small spikes at every sample clock
edge as the sample capacitor is connected to be charged.
The time constant of this combination is small, 2.5pF
100kΩ = 250ns, and during the 2.5µs period devoted to
sampling, ten time constants elapse. This allows each
sample to settle to within 46ppm and it is these samples
that are used to compute the RMS value.
This is a much higher accuracy than the LTC1966 conver-
sion limits, and far better than the accuracy computed via
the simplistic resistive divider model:
V V
R
R R
V
M
M k
V
IN SOURCE
IN
IN SOURCE
SOURCE
SOURCE
=
+
=
Ω
Ω + Ω
=
8
8 100
1 25 . %
Figure 24. LTC1966 Equivalent Analog Input Circuit
This resistive divider calculation does give the correct
model of what voltage is seen at the input terminals by a
parallel load averaged over a several clock cycles, which is
what a large shunt capacitor will do—average the current
spikes over several clock cycles.
When high source impedances are used, care must be taken
to minimize shunt capacitance at the LTC1966 input so as
not to increase the settling time. Shunt capacitance of just
2.5pF will double the input settling time constant and the
error in the above example grows from 46ppm to 0.67%
(6700ppm). A 13pF scope probe will increase the error
to almost 20%. As a consequence, it is important to not
try to filter the input with large input capacitances unless
driven by a low impedance. Keep time constant <<2.5µs.
When the LTC1966 is driven by op amp outputs, whose low
DC impedance can be compromised by sharp capacitive
load switching, a small series resistor may be added. A
10k resistor will easily settle with the 2.5pF input sampling
capacitor to within 1ppm.
These are important points to consider both during design
and debug. During lab debug, and even production testing,
a high value series resistor to any test point is advisable.
Output Impedance
The LTC1966 output impedance during operation is simi-
larly due to a switched capacitor action. In this case, 59pF
of on-chip capacitance operating at 100kHz translates into
170kΩ. The closed loop RMS-to-DC calculation cuts that
in half to the nominal 85kΩ specified.
In order to create a DC result, a large averaging capacitor
is required. Capacitive loading and time constants are not
an issue on the output.
IN1
V
DD
V
DD
V
SS
V
SS
R
SW
(TYP)
6k
C
EQ
2.5pF
(TYP)
C
EQ
2.5pF
(TYP)
I
IN1
IN2
I
IN2
1966 F24
R
SW
(TYP)
6k
IIN
VV
R
IIN
VV
R
RM
AVG
IN IN
EQ
AVG
IN IN
EQ
EQ
1
2
8
12
21
()
=
()
=
=
LTC1966
27
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applicaTions inForMaTion
However, resistive loading is an issue and the 10MΩ
impedance of a DMM or 10× scope probe will drag the
output down by –0.85% typ.
During shutdown, the switching action is halted and a
fixed 30k resistor shunts V
OUT
to OUT RTN so that C
AVE
is discharged.
Guard Ringing the Output
The LTC1966’s combination of precision and high output
impedance can present challenges that make the use of
a guard ring around the output a good idea for many ap-
plications.
As mentioned above, a 10M resistive loading to ground
will drag down the gain far more than the specificed gain
tolerance. On a printed circuit board, contaminants from
solder flux residue to finger grime can create parasitic
resistances, which may be very high impedance, but can
have deleterious effects on the realized accuracy. As an
example, if the output (Pin 5) is routed near V
SS
(Pin 4)
in a ±5V application, a parasitic resistance of 1G (1,000M)
is enough to introduce a –425µV output offset error, more
than the specified limit of the LTC1966 itself.
Use of a guard ring, wherein the LTC1966 output node is
completely surrounded by a low impedance voltage, can
reduce leakage related errors substantially. The ground
ring can be tied to OUTRTN (Pin 6) and should encircle the
output (Pin 5), the averaging capacitor terminal, and the
destination terminal at the ADC, filter op amp, or whatever
else may be next.
Figure 24a shows a sample PCB layout for the circuit of
Figure 13, wherein the guard ring trace encloses R1, R2,
and the terminals of C1, C2, and the op amp input con-
nected to the high impedance LTC1966 Output. For the
circuit of figure 14, the guard ring should enclose R1 and
the terminals of C1 and C2, as well as the terminal at the
ultimate destination.
Figure 24b shows a sample PCB layout for the circuit of
Figure 23. The summing node of the LT1494 has the same
high impedance and high accuracy as the LTC1966 output,
so here the guard ring encircles both of them. Any leakage
between them is benign because the LT1494 forces them
to the same nominal voltage.
Figure 24a. PCB Layout of Figure 13 with Guard Ring
Figure 24b. PCB Layout of Figure 23 with Guard Ring
1966 F24a
LTC1966
MS8
LT1880
SO8
0.1µF
0.1µF
1µFC
AVE
1966 F24b
LTC1966
MS8
LT1494
SO8
1µFC
AVE

LTC1966MPMS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC Prec uP, DS RMS-to-DC Conv
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