2004 Mar 04 28
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
7.23 I
2
C-bus format
Table 17 I
2
C-bus write access to control registers; see Table 23
Table 18 I
2
C-bus write access to the HD line count array (subaddress D0H); see Table 23
Table 19 I
2
C-bus write access to cursor bit map (subaddress FEH); see Table 23
Table 20 I
2
C-bus write access to colour look-up table (subaddress FFH); see Table 23
Table 21 I
2
C-bus read access to control registers; see Table 23
Table 22 I
2
C-bus read access to cursor bit map or colour LUT; see Table 23
Table 23 Explanations of Tables 17 to 22
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.
2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.
S 10001000 A SUBADDRESS A DATA 0 A -------- DATA n A P
S 10001000 A D0H A RAM ADDRESS A DATA 00 A DATA 01 A -------- DATA n A P
S 10001000 A FEH A RAM ADDRESS A DATA 0 A -------- DATA n A P
S 10001000 A FFH A RAM ADDRESS A DATA 0R A DATA 0G A DATA 0B A -------- P
S 10001000 A SUBADDRESS A Sr 10001001 A DATA0 Am -------- DATA n Am P
S 10001000 A FEH
or
FFH
A RAM ADDRESS A Sr 1 0 001001 A DATA0 Am -------- DATA n Am P
CODE DESCRIPTION
S START condition
Sr repeated START condition
1000100X; note 1 slave address
A acknowledge generated by the slave
Am acknowledge generated by the master
SUBADDRESS; note 2 subaddress byte
DATA data byte
-------- continued data bytes and acknowledges
P STOP condition
RAM ADDRESS start address for RAM access
