2004 Mar 04 4
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
2 GENERAL DESCRIPTION
The SAA7104E; SAA7105E is an advanced
next-generation video encoder which converts PC
graphics data at maximum 1280 × 1024 resolution
(optionally 1920 × 1080 interlaced) to PAL (50 Hz) or
NTSC (60 Hz) video signals. A programmable scaler and
anti-flicker filter (maximum 5 lines) ensures properly sized
and flicker-free TV display as CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters
(DACs) can output RGB signals together with a TTL
composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA
monitor can be connected to the RGB outputs and
separate H and V-syncs as well, thereby serving as an
auxiliary monitor at maximum 1280 × 1024
resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this
port can provide Y, P
B
and P
R
signals for HDTV monitors.
The device includes a sync/clock generator and on-chip
DACs.
All inputs intended to interface to the host graphics
controller are designed for low-voltage signals between
down to 1.1 V and up to 3.6 V.
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
DDA
analog supply voltage 3.15 3.3 3.45 V
V
DDD
digital supply voltage 3.15 3.3 3.45 V
I
DDA
analog supply current 1 110 115 mA
I
DDD
digital supply current 1 175 200 mA
V
i
input signal voltage levels TTL compatible
V
o(p-p)
analog CVBS output signal voltage for a 100/100
colour bar at 75/2 load (peak-to-peak value)
1.23 V
R
L
load resistance 37.5 −Ω
ILE
lf(DAC)
low frequency integral linearity error of DACs −−±3 LSB
DLE
lf(DAC)
low frequency differential linearity error of DACs −−±1 LSB
T
amb
ambient temperature 0 70 °C
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
SAA7104E BGA156 plastic ball grid array package; 156 balls; body
15 × 15 × 1.15 mm
SOT472-1
SAA7105E
2004 Mar 04 5
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
2004 Mar 04 5
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5 BLOCK DIAGRAM
VERTICAL
SCALER
VERTICAL
FILTER
HORIZONTAL
SCALER
DECIMATOR
4 : 4 : 4 to
4 : 2 : 2
TRIPLE
DAC
BLUE_CB_CVBS
TRST
DUMP
RSET
TDI
TDO
TMS
TCK
GREEN_VBS_CVBS
RED_CR_C_CVBS
C6
C7
C8
VSM
D7
HSM_CSYNC
D8
TVD
F12
BORDER
GENERATOR
FIFO
LUT
+
CURSOR
RGB TO Y-C
B
-C
R
MATRIX
FIFO
+
UPSAMPLING
VIDEO
ENCODER
HD
OUTPUT
I
2
C-BUS
CONTROL
CRYSTAL
OSCILLATOR
TIMING
GENERATOR
G1A6A5 C3
FSVGC
VSVGC
XTALO
27 MHz
TTX_SRES
XTALI
HSVGC
CBO TTXRQ_XCLKO2
F1 G3
G2
SDA SCL
E2 D2E3 C4
PIXEL CLOCK
SYNTHESIZER
INPUT
FORMATTER
V
DDA1
C1, C2, B1, B2,
A2, B4, B3, A3,
F3, H1,
H2, H3
A10, B9,
C9, D9
V
DDA2
B6
V
DDA3
D6
V
DDA4
B6
V
SSA1
B8
V
SSA2
A8
V
DDD1
F4
V
DDD2
D4
V
DDD3
D4
A4
A7, B7
A9
B5
D1
D3
E1
V
DDD4
D4
V
SSD1
C5, D5,
E4
V
SSD2
C5, D5,
E4
V
SSD3
C5, D5,
E4
V
SSD4
C5, D5,
E4
F2
PD11 to
PD0
PIXCLKI
G4
PIXCLKO
mhc572
SAA7104E
SAA7105E
RESET
Fig.1 Block diagram.
2004 Mar 04 6
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
6 PINNING
SYMBOL PIN TYPE
(1)
DESCRIPTION
PD7 A2 I MSB with C
B
-Y-C
R
4 : 2 : 2; see Tables 9 to 14 for pin assignment
PD4 A3 I MSB 3 with C
B
-Y-C
R
4 : 2 : 2; see Tables 9 to 14 for
pin assignment
TRST A4 I/pu test reset input for BST; active LOW; notes 2, 3 and 4
XTALI A5 I crystal oscillator input
XTALO A6 O crystal oscillator output
DUMP A7, B7 O DAC reference pin; connected via 12 resistor to analog ground
V
SSA2
A8 S analog ground 2
RSET A9 O DAC reference pin; connected via 1 k resistor to analog ground
(do not use capacitor in parallel with 1 k resistor)
V
DDA1
A10, B9, C9, D9 S analog supply voltage 1 (3.3 V for DACs)
PD9 B1 I see Tables 9 to 14 for pin assignment
PD8 B2 I see Tables 9 to 14 for pin assignment
PD5 B3 I MSB 2 with C
B
-Y-C
R
4 : 2 : 2; see Tables 9 to 14 for
pin assignment
PD6 B4 I MSB 1 with C
B
-Y-C
R
4 : 2 : 2; see Tables 9 to 14 for
pin assignment
TDI B5 I test data input for BST; note 2
V
DDA2
B6 S analog supply voltage 2 (3.3 V for DACs)
V
DDA4
B6 S analog supply voltage 4 (3.3 V)
V
SSA1
B8 S analog ground 1
PD11 C1 I see Tables 9 to 14 for pin assignment
PD10 C2 I see Tables 9 to 14 for pin assignment
TTX_SRES C3 I teletext input or sync reset input
TTXRQ_XCLKO2 C4 O teletext request output or 13.5 MHz clock output of the crystal
oscillator; note 5
V
SSD1
C5, D5, E4 S digital ground 1
V
SSD2
C5, D5, E4 S digital ground 2
V
SSD3
C5, D5, E4 S digital ground 3
V
SSD4
C5, D5, E4 S digital ground 4
BLUE_CB_CVBS C6 O analog output of BLUE or C
B
or CVBS signal
GREEN_VBS_CVBS C7 O analog output of GREEN or VBS or CVBS signal
RED_CR_C_CVBS C8 O analog output of RED or C
R
or C or CVBS signal
TDO D1 O test data output for BST; note 2
RESET D2 I reset input; active LOW
TMS D3 I/pu test mode select input for Boundary Scan Test (BST); note 2
V
DDD2
D4 S digital supply voltage 2 (3.3 V for I/Os)
V
DDD3
D4 S digital supply voltage 3 (3.3 V for core)
V
DDD4
D4 S digital supply voltage 4 (3.3 V for core)
V
DDA3
D6 S analog supply voltage 3 (3.3 V for oscillator)

SAA7105E/V1/S1,557

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC DIGITAL VIDEO ENCODER 156LBGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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